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dkim=none (message not signed) header.d=none;nongnu.org; dmarc=none action=none header.from=os.amperecomputing.com; Received: from SN6PR01MB4304.prod.exchangelabs.com (2603:10b6:805:a6::23) by SN6PR01MB3823.prod.exchangelabs.com (2603:10b6:805:19::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3153.28; Tue, 7 Jul 2020 15:26:36 +0000 Received: from SN6PR01MB4304.prod.exchangelabs.com ([fe80::3daa:94bb:9223:161f]) by SN6PR01MB4304.prod.exchangelabs.com ([fe80::3daa:94bb:9223:161f%5]) with mapi id 15.20.3153.029; Tue, 7 Jul 2020 15:26:36 +0000 From: Aaron Lindsay To: qemu-devel@nongnu.org, Peter Maydell Cc: Aaron Lindsay Subject: [PATCH] target/arm: Don't do raw writes for PMINTENCLR Date: Tue, 7 Jul 2020 11:26:16 -0400 Message-Id: <20200707152616.1917154-1-aaron@os.amperecomputing.com> X-Mailer: git-send-email 2.27.0 X-ClientProxiedBy: CY4PR1201CA0021.namprd12.prod.outlook.com (2603:10b6:910:16::31) To SN6PR01MB4304.prod.exchangelabs.com (2603:10b6:805:a6::23) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from strawberry.amperecomputing.com (68.73.113.219) by CY4PR1201CA0021.namprd12.prod.outlook.com (2603:10b6:910:16::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3174.20 via Frontend Transport; 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envelope-from=aaron@os.amperecomputing.com; helo=NAM10-BN7-obe.outbound.protection.outlook.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/07 11:41:40 X-ACL-Warn: Detected OS = Windows NT kernel [generic] [fuzzy] X-Spam_score_int: -36 X-Spam_score: -3.7 X-Spam_bar: --- X-Spam_report: (-3.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, MSGID_FROM_MTA_HEADER=0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Raw writes to this register when in KVM mode can cause interrupts to be raised (even when the PMU is disabled). Because the underlying state is already aliased to PMINTENSET (which already provides raw write functions), we can safely disable raw accesses to PMINTENCLR entirely. Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index dc9c29f998..c69a2baf1d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2269,13 +2269,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .resetvalue = 0x0 }, { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, .access = PL1_RW, .accessfn = access_tpm, - .type = ARM_CP_ALIAS | ARM_CP_IO, + .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), .writefn = pmintenclr_write, }, { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, .access = PL1_RW, .accessfn = access_tpm, - .type = ARM_CP_ALIAS | ARM_CP_IO, + .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), .writefn = pmintenclr_write }, { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,