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[82.1.209.49]) by smtp.gmail.com with ESMTPSA id y5sm24225932wrs.63.2020.06.08.04.40.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jun 2020 04:40:32 -0700 (PDT) From: Leif Lindholm To: QEMU Developers Subject: [RFC PATCH 3/3] target/arm: use cortex...common_init for cpu64 max Date: Mon, 8 Jun 2020 12:40:28 +0100 Message-Id: <20200608114028.25345-4-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200608114028.25345-1-leif@nuviainc.com> References: <20200608114028.25345-1-leif@nuviainc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=leif@nuviainc.com; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Andrew Jones , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Drop the call to aarch64_a57_initfn from aarch64_max_initfn, replacing it with calls to aarch64_cpu_common_init and cortex_a72_a57_a53_common_init. Cache and GIC configuration is now set directly, using aarch64_a72_initfn as a template. Set cpu->dtb_compatible to "qemu,aarch64-max". This has the following effects apart from the ones mentioned above: - kvm_target will no longer be explicitly initialized for cpu max in tcg mode. - id_mmfr0 will now be set to an architecturally permitted value. - define_arm_cp_regs() is no longer called, since those registers are implementation defined and specific to the supported cortex-a processors. Signed-off-by: Leif Lindholm --- target/arm/cpu64.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 9927c1f75d..452efe78bf 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -561,26 +561,20 @@ static void aarch64_max_initfn(Object *obj) } else { uint64_t t; uint32_t u; - aarch64_a57_initfn(obj); + cpu->dtb_compatible = "qemu,aarch64-max"; /* * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real * one and try to apply errata workarounds or use impdef features we * don't provide. * An IMPLEMENTER field of 0 means "reserved for software use"; - * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers - * to see which features are present"; * the VARIANT, PARTNUM and REVISION fields are all implementation * defined and we choose to define PARTNUM just in case guest * code needs to distinguish this QEMU CPU from other software * implementations, though this shouldn't be needed. */ - t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); - t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); - t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); - t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0); - t = FIELD_DP64(t, MIDR_EL1, REVISION, 0); - cpu->midr = t; + aarch64_cpu_common_init(obj, 0, 'Q', 0, 0); + cortex_a72_a57_a53_common_init(cpu); t = cpu->isar.id_aa64isar0; t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ @@ -680,12 +674,24 @@ static void aarch64_max_initfn(Object *obj) * and enabling SVE in system mode is more useful in the short term. */ + cpu->reset_fpsid = 0x41034080; + cpu->clidr = 0x0a200023; + cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ + cpu->gic_num_lrs = 4; + cpu->gic_vpribits = 5; + cpu->gic_vprebits = 5; + #ifdef CONFIG_USER_ONLY /* For usermode -cpu max we can use a larger and more efficient DCZ * blocksize since we don't have to follow what the hardware does. */ cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ +#else + cpu->ctr = 0x8444c004; + cpu->dcz_blocksize = 4; /* 64 bytes */ #endif }