diff mbox series

[v6,18/20] hw/block/nvme: factor out pmr setup

Message ID 20200514044611.734782-19-its@irrelevant.dk
State New
Headers show
Series nvme: small fixes, refactoring and cleanups | expand

Commit Message

Klaus Jensen May 14, 2020, 4:46 a.m. UTC 
From: Klaus Jensen <k.jensen@samsung.com>

Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
---
 hw/block/nvme.c | 95 ++++++++++++++++++++++++++-----------------------
 1 file changed, 51 insertions(+), 44 deletions(-)

Comments

Philippe Mathieu-Daudé May 14, 2020, 7:59 a.m. UTC | #1 
On 5/14/20 6:46 AM, Klaus Jensen wrote:
> From: Klaus Jensen <k.jensen@samsung.com>
> 
> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
> Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
> ---
>   hw/block/nvme.c | 95 ++++++++++++++++++++++++++-----------------------
>   1 file changed, 51 insertions(+), 44 deletions(-)
> 
> diff --git a/hw/block/nvme.c b/hw/block/nvme.c
> index d71a5f142d51..7254b66ae199 100644
> --- a/hw/block/nvme.c
> +++ b/hw/block/nvme.c
> @@ -58,6 +58,7 @@
>   #define NVME_REG_SIZE 0x1000
>   #define NVME_DB_SIZE  4
>   #define NVME_CMB_BIR 2
> +#define NVME_PMR_BIR 2
>   
>   #define NVME_GUEST_ERR(trace, fmt, ...) \
>       do { \
> @@ -1463,6 +1464,55 @@ static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev)
>                        PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem);
>   }
>   
> +static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
> +{
> +    /* Controller Capabilities register */
> +    NVME_CAP_SET_PMRS(n->bar.cap, 1);
> +
> +    /* PMR Capabities register */
> +    n->bar.pmrcap = 0;
> +    NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0);
> +    NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0);
> +    NVME_PMRCAP_SET_BIR(n->bar.pmrcap, NVME_PMR_BIR);
> +    NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0);
> +    /* Turn on bit 1 support */
> +    NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02);
> +    NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0);
> +    NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0);
> +
> +    /* PMR Control register */
> +    n->bar.pmrctl = 0;
> +    NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0);
> +
> +    /* PMR Status register */
> +    n->bar.pmrsts = 0;
> +    NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0);
> +    NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0);
> +    NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0);
> +    NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0);
> +
> +    /* PMR Elasticity Buffer Size register */
> +    n->bar.pmrebs = 0;
> +    NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0);
> +    NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0);
> +    NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0);
> +
> +    /* PMR Sustained Write Throughput register */
> +    n->bar.pmrswtp = 0;
> +    NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0);
> +    NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0);
> +
> +    /* PMR Memory Space Control register */
> +    n->bar.pmrmsc = 0;
> +    NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0);
> +    NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0);
> +
> +    pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap),
> +                     PCI_BASE_ADDRESS_SPACE_MEMORY |
> +                     PCI_BASE_ADDRESS_MEM_TYPE_64 |
> +                     PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmrdev->mr);
> +}
> +
>   static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev)
>   {
>       uint8_t *pci_conf = pci_dev->config;
> @@ -1541,50 +1591,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
>       if (n->params.cmb_size_mb) {
>           nvme_init_cmb(n, pci_dev);
>       } else if (n->pmrdev) {
> -        /* Controller Capabilities register */
> -        NVME_CAP_SET_PMRS(n->bar.cap, 1);
> -
> -        /* PMR Capabities register */
> -        n->bar.pmrcap = 0;
> -        NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0);
> -        NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0);
> -        NVME_PMRCAP_SET_BIR(n->bar.pmrcap, 2);
> -        NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0);
> -        /* Turn on bit 1 support */
> -        NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02);
> -        NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0);
> -        NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0);
> -
> -        /* PMR Control register */
> -        n->bar.pmrctl = 0;
> -        NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0);
> -
> -        /* PMR Status register */
> -        n->bar.pmrsts = 0;
> -        NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0);
> -        NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0);
> -        NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0);
> -        NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0);
> -
> -        /* PMR Elasticity Buffer Size register */
> -        n->bar.pmrebs = 0;
> -        NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0);
> -        NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0);
> -        NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0);
> -
> -        /* PMR Sustained Write Throughput register */
> -        n->bar.pmrswtp = 0;
> -        NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0);
> -        NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0);
> -
> -        /* PMR Memory Space Control register */
> -        n->bar.pmrmsc = 0;
> -        NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0);
> -        NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0);
> -
> -        pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap),
> -            PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64 |
> -            PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmrdev->mr);
> +        nvme_init_pmr(n, pci_dev);
>       }
>   
>       for (i = 0; i < n->num_namespaces; i++) {
> 

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
diff mbox series

Patch

diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index d71a5f142d51..7254b66ae199 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -58,6 +58,7 @@ 
 #define NVME_REG_SIZE 0x1000
 #define NVME_DB_SIZE  4
 #define NVME_CMB_BIR 2
+#define NVME_PMR_BIR 2
 
 #define NVME_GUEST_ERR(trace, fmt, ...) \
     do { \
@@ -1463,6 +1464,55 @@  static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev)
                      PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem);
 }
 
+static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
+{
+    /* Controller Capabilities register */
+    NVME_CAP_SET_PMRS(n->bar.cap, 1);
+
+    /* PMR Capabities register */
+    n->bar.pmrcap = 0;
+    NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0);
+    NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0);
+    NVME_PMRCAP_SET_BIR(n->bar.pmrcap, NVME_PMR_BIR);
+    NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0);
+    /* Turn on bit 1 support */
+    NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02);
+    NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0);
+    NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0);
+
+    /* PMR Control register */
+    n->bar.pmrctl = 0;
+    NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0);
+
+    /* PMR Status register */
+    n->bar.pmrsts = 0;
+    NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0);
+    NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0);
+    NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0);
+    NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0);
+
+    /* PMR Elasticity Buffer Size register */
+    n->bar.pmrebs = 0;
+    NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0);
+    NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0);
+    NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0);
+
+    /* PMR Sustained Write Throughput register */
+    n->bar.pmrswtp = 0;
+    NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0);
+    NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0);
+
+    /* PMR Memory Space Control register */
+    n->bar.pmrmsc = 0;
+    NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0);
+    NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0);
+
+    pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap),
+                     PCI_BASE_ADDRESS_SPACE_MEMORY |
+                     PCI_BASE_ADDRESS_MEM_TYPE_64 |
+                     PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmrdev->mr);
+}
+
 static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev)
 {
     uint8_t *pci_conf = pci_dev->config;
@@ -1541,50 +1591,7 @@  static void nvme_realize(PCIDevice *pci_dev, Error **errp)
     if (n->params.cmb_size_mb) {
         nvme_init_cmb(n, pci_dev);
     } else if (n->pmrdev) {
-        /* Controller Capabilities register */
-        NVME_CAP_SET_PMRS(n->bar.cap, 1);
-
-        /* PMR Capabities register */
-        n->bar.pmrcap = 0;
-        NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0);
-        NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0);
-        NVME_PMRCAP_SET_BIR(n->bar.pmrcap, 2);
-        NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0);
-        /* Turn on bit 1 support */
-        NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02);
-        NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0);
-        NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0);
-
-        /* PMR Control register */
-        n->bar.pmrctl = 0;
-        NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0);
-
-        /* PMR Status register */
-        n->bar.pmrsts = 0;
-        NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0);
-        NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0);
-        NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0);
-        NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0);
-
-        /* PMR Elasticity Buffer Size register */
-        n->bar.pmrebs = 0;
-        NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0);
-        NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0);
-        NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0);
-
-        /* PMR Sustained Write Throughput register */
-        n->bar.pmrswtp = 0;
-        NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0);
-        NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0);
-
-        /* PMR Memory Space Control register */
-        n->bar.pmrmsc = 0;
-        NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0);
-        NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0);
-
-        pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap),
-            PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64 |
-            PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmrdev->mr);
+        nvme_init_pmr(n, pci_dev);
     }
 
     for (i = 0; i < n->num_namespaces; i++) {