From patchwork Thu Apr 30 07:21:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 1279989 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=2001:470:142::17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=c-sky.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:470:142::17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49CRhc6YnZz9sSg for ; Thu, 30 Apr 2020 17:24:15 +1000 (AEST) Received: from localhost ([::1]:48628 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU3YL-0004xc-8b for incoming@patchwork.ozlabs.org; Thu, 30 Apr 2020 03:24:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34256) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU3XW-0004Zm-Os for qemu-devel@nongnu.org; Thu, 30 Apr 2020 03:23:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU3W7-0006Y2-8i for qemu-devel@nongnu.org; Thu, 30 Apr 2020 03:23:22 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:53190) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jU3W6-0006Wn-Kj; Thu, 30 Apr 2020 03:21:54 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1414109|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0183836-0.00115908-0.980457; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03300; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.HQfovas_1588231302; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.HQfovas_1588231302) by smtp.aliyun-inc.com(10.147.40.7); Thu, 30 Apr 2020 15:21:44 +0800 From: LIU Zhiwei To: peter.maydell@linaro.org Subject: [RFC PATCH 3/8] riscv: Define riscv struct reginfo Date: Thu, 30 Apr 2020 15:21:34 +0800 Message-Id: <20200430072139.4602-4-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200430072139.4602-1-zhiwei_liu@c-sky.com> References: <20200430072139.4602-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/30 03:21:44 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, palmer@dabbelt.com, alistair23@gmail.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: LIU Zhiwei --- risu_reginfo_riscv64.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 risu_reginfo_riscv64.h diff --git a/risu_reginfo_riscv64.h b/risu_reginfo_riscv64.h new file mode 100644 index 0000000..7d365a8 --- /dev/null +++ b/risu_reginfo_riscv64.h @@ -0,0 +1,29 @@ +/****************************************************************************** + * Copyright (c) 2020 PingTouGe Semiconductor + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * LIU Zhiwei(PingTouGe) - initial implementation + * based on Peter Maydell's risu_arm.c + *****************************************************************************/ + +#ifndef RISU_REGINFO_RISCV64_H +#define RISU_REGINFO_RISCV64_H + +struct reginfo { + uint64_t fault_address; + uint64_t regs[32]; + uint64_t fregs[32]; + uint64_t sp; + uint64_t pc; + uint32_t flags; + uint32_t faulting_insn; + + /* FP */ + uint32_t fcsr; +}; + +#endif /* RISU_REGINFO_RISCV64_H */