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[14.202.190.183]) by smtp.gmail.com with ESMTPSA id 93sm4609599pjo.43.2020.03.25.07.42.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Mar 2020 07:42:56 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Subject: [PATCH 5/5] ppc/pnv: Implement mce injection Date: Thu, 26 Mar 2020 00:41:47 +1000 Message-Id: <20200325144147.221875-6-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200325144147.221875-1-npiggin@gmail.com> References: <20200325144147.221875-1-npiggin@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexey Kardashevskiy , Mahesh Salgaonkar , qemu-devel@nongnu.org, Nicholas Piggin , Greg Kurz , =?utf-8?b?Q8OpZHJp?= =?utf-8?q?c_Le_Goater?= , Ganesh Goudar , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This implements mce injection for pnv. Signed-off-by: Nicholas Piggin --- hw/ppc/pnv.c | 55 ++++++++++++++++++++++++++++++++++++++++ target/ppc/cpu.h | 1 + target/ppc/excp_helper.c | 12 +++++++++ 3 files changed, 68 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 671535ebe6..9c515bfeed 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -38,6 +38,7 @@ #include "hw/nmi.h" #include "exec/address-spaces.h" #include "qapi/visitor.h" +#include "qapi/qmp/qdict.h" #include "monitor/monitor.h" #include "hw/intc/intc.h" #include "hw/ipmi/ipmi.h" @@ -1981,11 +1982,63 @@ static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) } } +typedef struct MCEInjectionParams { + uint64_t srr1_mask; + uint32_t dsisr; + uint64_t dar; + bool recovered; +} MCEInjectionParams; + +static void pnv_do_mce_on_cpu(CPUState *cs, run_on_cpu_data data) +{ + MCEInjectionParams *params = data.host_ptr; + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + uint64_t srr1_mce_bits = PPC_BITMASK(42, 45) | PPC_BIT(36); + + cpu_synchronize_state(cs); + ppc_cpu_do_machine_check(cs); + + env->spr[SPR_SRR1] |= (params->srr1_mask & srr1_mce_bits); + if (params->dsisr) { + env->spr[SPR_DSISR] = params->dsisr; + env->spr[SPR_DAR] = params->dar; + } + + if (!params->recovered) { + env->msr &= ~MSR_RI; + } +} + +static void pnv_mce(MCEState *m, const QDict *qdict, Error **errp) +{ + int cpu_index = qdict_get_int(qdict, "cpu_index"); + uint64_t srr1_mask = qdict_get_int(qdict, "srr1_mask"); + uint32_t dsisr = qdict_get_int(qdict, "dsisr"); + uint64_t dar = qdict_get_int(qdict, "dar"); + bool recovered = qdict_get_int(qdict, "recovered"); + CPUState *cs; + + cs = qemu_get_cpu(cpu_index); + + if (cs != NULL) { + MCEInjectionParams params = { + .srr1_mask = srr1_mask, + .dsisr = dsisr, + .dar = dar, + .recovered = recovered, + }; + + run_on_cpu(cs, pnv_do_mce_on_cpu, RUN_ON_CPU_HOST_PTR(¶ms)); + } +} + static void pnv_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); NMIClass *nc = NMI_CLASS(oc); + MCEClass *mcec = MCE_CLASS(oc); mc->desc = "IBM PowerNV (Non-Virtualized)"; mc->init = pnv_init; @@ -2003,6 +2056,7 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data) mc->default_ram_id = "pnv.ram"; ispc->print_info = pnv_pic_print_info; nc->nmi_monitor_handler = pnv_nmi; + mcec->mce_monitor_handler = pnv_mce; object_class_property_add_bool(oc, "hb-mode", pnv_machine_get_hb, pnv_machine_set_hb, @@ -2067,6 +2121,7 @@ static const TypeInfo types[] = { .interfaces = (InterfaceInfo[]) { { TYPE_INTERRUPT_STATS_PROVIDER }, { TYPE_NMI }, + { TYPE_MCE }, }, }, { diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f4a5304d43..9be27f59c5 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1221,6 +1221,7 @@ int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, void *opaque); #ifndef CONFIG_USER_ONLY void ppc_cpu_do_system_reset(CPUState *cs); +void ppc_cpu_do_machine_check(CPUState *cs); void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector); extern const VMStateDescription vmstate_ppc_cpu; #endif diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 7f2b5899d3..81dd8b6f8e 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -279,6 +279,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) cs->halted = 1; cpu_interrupt_exittb(cs); } + if (msr_pow) { + /* indicate that we resumed from power save mode */ + msr |= 0x10000; + } if (env->msr_mask & MSR_HVB) { /* * ISA specifies HV, but can be delivered to guest with HV @@ -969,6 +973,14 @@ void ppc_cpu_do_system_reset(CPUState *cs) powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET); } +void ppc_cpu_do_machine_check(CPUState *cs) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_MCHECK); +} + void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector) { PowerPCCPU *cpu = POWERPC_CPU(cs);