Message ID | 20200316142928.153431-16-its@irrelevant.dk |
---|---|
State | New |
Headers | show |
Series | nvme: support NVMe v1.3d, SGLs and multiple namespaces | expand |
On Mon, 2020-03-16 at 07:29 -0700, Klaus Jensen wrote: > From: Klaus Jensen <k.jensen@samsung.com> > > Add additional trace calls for nvme_enqueue_req_completion, mmio and > doorbell writes. > > Also, streamline nvme_identify_ns and nvme_identify_ns_list. They do not > need to repeat the command, it is already in the trace name. > > Signed-off-by: Klaus Jensen <k.jensen@samsung.com> > Acked-by: Keith Busch <kbusch@kernel.org> > --- > hw/block/nvme.c | 10 ++++++++++ > hw/block/trace-events | 9 +++++++-- > 2 files changed, 17 insertions(+), 2 deletions(-) > > diff --git a/hw/block/nvme.c b/hw/block/nvme.c > index eb9c722df968..85c7c86b35f0 100644 > --- a/hw/block/nvme.c > +++ b/hw/block/nvme.c > @@ -320,6 +320,8 @@ static void nvme_post_cqes(void *opaque) > static void nvme_enqueue_req_completion(NvmeCQueue *cq, NvmeRequest *req) > { > assert(cq->cqid == req->sq->cqid); > + trace_nvme_dev_enqueue_req_completion(nvme_cid(req), cq->cqid, > + req->status); > QTAILQ_REMOVE(&req->sq->out_req_list, req, entry); > QTAILQ_INSERT_TAIL(&cq->req_list, req, entry); > timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500); > @@ -1527,6 +1529,8 @@ static uint64_t nvme_mmio_read(void *opaque, hwaddr addr, unsigned size) > uint8_t *ptr = (uint8_t *)&n->bar; > uint64_t val = 0; > > + trace_nvme_dev_mmio_read(addr); > + > if (unlikely(addr & (sizeof(uint32_t) - 1))) { > NVME_GUEST_ERR(nvme_dev_ub_mmiord_misaligned32, > "MMIO read not 32-bit aligned," > @@ -1601,6 +1605,8 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val) > return; > } > > + trace_nvme_dev_mmio_doorbell_cq(cq->cqid, new_head); > + > start_sqs = nvme_cq_full(cq) ? 1 : 0; > cq->head = new_head; > if (start_sqs) { > @@ -1653,6 +1659,8 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val) > return; > } > > + trace_nvme_dev_mmio_doorbell_sq(sq->sqid, new_tail); > + > sq->tail = new_tail; > timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500); > } > @@ -1661,6 +1669,8 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val) > static void nvme_mmio_write(void *opaque, hwaddr addr, uint64_t data, > unsigned size) > { > + trace_nvme_dev_mmio_write(addr, data); > + > NvmeCtrl *n = (NvmeCtrl *)opaque; > if (addr < sizeof(n->bar)) { > nvme_write_bar(n, addr, data, size); > diff --git a/hw/block/trace-events b/hw/block/trace-events > index 4cf39961989d..dde1d22bc39a 100644 > --- a/hw/block/trace-events > +++ b/hw/block/trace-events > @@ -39,8 +39,8 @@ nvme_dev_create_cq(uint64_t addr, uint16_t cqid, uint16_t vector, uint16_t size, > nvme_dev_del_sq(uint16_t qid) "deleting submission queue sqid=%"PRIu16"" > nvme_dev_del_cq(uint16_t cqid) "deleted completion queue, sqid=%"PRIu16"" > nvme_dev_identify_ctrl(void) "identify controller" > -nvme_dev_identify_ns(uint16_t ns) "identify namespace, nsid=%"PRIu16"" > -nvme_dev_identify_nslist(uint16_t ns) "identify namespace list, nsid=%"PRIu16"" > +nvme_dev_identify_ns(uint32_t ns) "nsid %"PRIu32"" > +nvme_dev_identify_nslist(uint32_t ns) "nsid %"PRIu32"" > nvme_dev_getfeat(uint16_t cid, uint32_t fid) "cid %"PRIu16" fid 0x%"PRIx32"" > nvme_dev_setfeat(uint16_t cid, uint32_t fid, uint32_t val) "cid %"PRIu16" fid 0x%"PRIx32" val 0x%"PRIx32"" > nvme_dev_getfeat_vwcache(const char* result) "get feature volatile write cache, result=%s" > @@ -54,10 +54,13 @@ nvme_dev_aer(uint16_t cid) "cid %"PRIu16"" > nvme_dev_aer_aerl_exceeded(void) "aerl exceeded" > nvme_dev_aer_masked(uint8_t type, uint8_t mask) "type 0x%"PRIx8" mask 0x%"PRIx8"" > nvme_dev_aer_post_cqe(uint8_t typ, uint8_t info, uint8_t log_page) "type 0x%"PRIx8" info 0x%"PRIx8" lid 0x%"PRIx8"" > +nvme_dev_enqueue_req_completion(uint16_t cid, uint16_t cqid, uint16_t status) "cid %"PRIu16" cqid %"PRIu16" status 0x%"PRIx16"" > nvme_dev_enqueue_event(uint8_t typ, uint8_t info, uint8_t log_page) "type 0x%"PRIx8" info 0x%"PRIx8" lid 0x%"PRIx8"" > nvme_dev_enqueue_event_noqueue(int queued) "queued %d" > nvme_dev_enqueue_event_masked(uint8_t typ) "type 0x%"PRIx8"" > nvme_dev_no_outstanding_aers(void) "ignoring event; no outstanding AERs" > +nvme_dev_mmio_read(uint64_t addr) "addr 0x%"PRIx64"" > +nvme_dev_mmio_write(uint64_t addr, uint64_t data) "addr 0x%"PRIx64" data 0x%"PRIx64"" > nvme_dev_mmio_intm_set(uint64_t data, uint64_t new_mask) "wrote MMIO, interrupt mask set, data=0x%"PRIx64", new_mask=0x%"PRIx64"" > nvme_dev_mmio_intm_clr(uint64_t data, uint64_t new_mask) "wrote MMIO, interrupt mask clr, data=0x%"PRIx64", new_mask=0x%"PRIx64"" > nvme_dev_mmio_cfg(uint64_t data) "wrote MMIO, config controller config=0x%"PRIx64"" > @@ -70,6 +73,8 @@ nvme_dev_mmio_start_success(void) "setting controller enable bit succeeded" > nvme_dev_mmio_stopped(void) "cleared controller enable bit" > nvme_dev_mmio_shutdown_set(void) "shutdown bit set" > nvme_dev_mmio_shutdown_cleared(void) "shutdown bit cleared" > +nvme_dev_mmio_doorbell_cq(uint16_t cqid, uint16_t new_head) "cqid %"PRIu16" new_head %"PRIu16"" > +nvme_dev_mmio_doorbell_sq(uint16_t sqid, uint16_t new_tail) "cqid %"PRIu16" new_tail %"PRIu16"" > > # nvme traces for error conditions > nvme_dev_err_invalid_dma(void) "PRP/SGL is too small for transfer size" Looks good. Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com> Best regards, Maxim Levitsky
diff --git a/hw/block/nvme.c b/hw/block/nvme.c index eb9c722df968..85c7c86b35f0 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -320,6 +320,8 @@ static void nvme_post_cqes(void *opaque) static void nvme_enqueue_req_completion(NvmeCQueue *cq, NvmeRequest *req) { assert(cq->cqid == req->sq->cqid); + trace_nvme_dev_enqueue_req_completion(nvme_cid(req), cq->cqid, + req->status); QTAILQ_REMOVE(&req->sq->out_req_list, req, entry); QTAILQ_INSERT_TAIL(&cq->req_list, req, entry); timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500); @@ -1527,6 +1529,8 @@ static uint64_t nvme_mmio_read(void *opaque, hwaddr addr, unsigned size) uint8_t *ptr = (uint8_t *)&n->bar; uint64_t val = 0; + trace_nvme_dev_mmio_read(addr); + if (unlikely(addr & (sizeof(uint32_t) - 1))) { NVME_GUEST_ERR(nvme_dev_ub_mmiord_misaligned32, "MMIO read not 32-bit aligned," @@ -1601,6 +1605,8 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val) return; } + trace_nvme_dev_mmio_doorbell_cq(cq->cqid, new_head); + start_sqs = nvme_cq_full(cq) ? 1 : 0; cq->head = new_head; if (start_sqs) { @@ -1653,6 +1659,8 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val) return; } + trace_nvme_dev_mmio_doorbell_sq(sq->sqid, new_tail); + sq->tail = new_tail; timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500); } @@ -1661,6 +1669,8 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val) static void nvme_mmio_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { + trace_nvme_dev_mmio_write(addr, data); + NvmeCtrl *n = (NvmeCtrl *)opaque; if (addr < sizeof(n->bar)) { nvme_write_bar(n, addr, data, size); diff --git a/hw/block/trace-events b/hw/block/trace-events index 4cf39961989d..dde1d22bc39a 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -39,8 +39,8 @@ nvme_dev_create_cq(uint64_t addr, uint16_t cqid, uint16_t vector, uint16_t size, nvme_dev_del_sq(uint16_t qid) "deleting submission queue sqid=%"PRIu16"" nvme_dev_del_cq(uint16_t cqid) "deleted completion queue, sqid=%"PRIu16"" nvme_dev_identify_ctrl(void) "identify controller" -nvme_dev_identify_ns(uint16_t ns) "identify namespace, nsid=%"PRIu16"" -nvme_dev_identify_nslist(uint16_t ns) "identify namespace list, nsid=%"PRIu16"" +nvme_dev_identify_ns(uint32_t ns) "nsid %"PRIu32"" +nvme_dev_identify_nslist(uint32_t ns) "nsid %"PRIu32"" nvme_dev_getfeat(uint16_t cid, uint32_t fid) "cid %"PRIu16" fid 0x%"PRIx32"" nvme_dev_setfeat(uint16_t cid, uint32_t fid, uint32_t val) "cid %"PRIu16" fid 0x%"PRIx32" val 0x%"PRIx32"" nvme_dev_getfeat_vwcache(const char* result) "get feature volatile write cache, result=%s" @@ -54,10 +54,13 @@ nvme_dev_aer(uint16_t cid) "cid %"PRIu16"" nvme_dev_aer_aerl_exceeded(void) "aerl exceeded" nvme_dev_aer_masked(uint8_t type, uint8_t mask) "type 0x%"PRIx8" mask 0x%"PRIx8"" nvme_dev_aer_post_cqe(uint8_t typ, uint8_t info, uint8_t log_page) "type 0x%"PRIx8" info 0x%"PRIx8" lid 0x%"PRIx8"" +nvme_dev_enqueue_req_completion(uint16_t cid, uint16_t cqid, uint16_t status) "cid %"PRIu16" cqid %"PRIu16" status 0x%"PRIx16"" nvme_dev_enqueue_event(uint8_t typ, uint8_t info, uint8_t log_page) "type 0x%"PRIx8" info 0x%"PRIx8" lid 0x%"PRIx8"" nvme_dev_enqueue_event_noqueue(int queued) "queued %d" nvme_dev_enqueue_event_masked(uint8_t typ) "type 0x%"PRIx8"" nvme_dev_no_outstanding_aers(void) "ignoring event; no outstanding AERs" +nvme_dev_mmio_read(uint64_t addr) "addr 0x%"PRIx64"" +nvme_dev_mmio_write(uint64_t addr, uint64_t data) "addr 0x%"PRIx64" data 0x%"PRIx64"" nvme_dev_mmio_intm_set(uint64_t data, uint64_t new_mask) "wrote MMIO, interrupt mask set, data=0x%"PRIx64", new_mask=0x%"PRIx64"" nvme_dev_mmio_intm_clr(uint64_t data, uint64_t new_mask) "wrote MMIO, interrupt mask clr, data=0x%"PRIx64", new_mask=0x%"PRIx64"" nvme_dev_mmio_cfg(uint64_t data) "wrote MMIO, config controller config=0x%"PRIx64"" @@ -70,6 +73,8 @@ nvme_dev_mmio_start_success(void) "setting controller enable bit succeeded" nvme_dev_mmio_stopped(void) "cleared controller enable bit" nvme_dev_mmio_shutdown_set(void) "shutdown bit set" nvme_dev_mmio_shutdown_cleared(void) "shutdown bit cleared" +nvme_dev_mmio_doorbell_cq(uint16_t cqid, uint16_t new_head) "cqid %"PRIu16" new_head %"PRIu16"" +nvme_dev_mmio_doorbell_sq(uint16_t sqid, uint16_t new_tail) "cqid %"PRIu16" new_tail %"PRIu16"" # nvme traces for error conditions nvme_dev_err_invalid_dma(void) "PRP/SGL is too small for transfer size"