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Fri, 13 Mar 2020 00:50:08 +0800 From: LIU Zhiwei To: richard.henderson@linaro.org, alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Subject: [PATCH v5 55/60] target/riscv: integer scalar move instruction Date: Thu, 12 Mar 2020 22:58:55 +0800 Message-Id: <20200312145900.2054-56-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200312145900.2054-1-zhiwei_liu@c-sky.com> References: <20200312145900.2054-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, LIU Zhiwei Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 5 +++++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 26 +++++++++++++++++++++++++ target/riscv/vector_helper.c | 15 ++++++++++++++ 4 files changed, 47 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index d94347a9a5..41cecd266c 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1106,3 +1106,8 @@ DEF_HELPER_3(vext_x_v_b, tl, ptr, tl, env) DEF_HELPER_3(vext_x_v_h, tl, ptr, tl, env) DEF_HELPER_3(vext_x_v_w, tl, ptr, tl, env) DEF_HELPER_3(vext_x_v_d, tl, ptr, tl, env) + +DEF_HELPER_3(vmv_s_x_b, void, ptr, tl, env) +DEF_HELPER_3(vmv_s_x_h, void, ptr, tl, env) +DEF_HELPER_3(vmv_s_x_w, void, ptr, tl, env) +DEF_HELPER_3(vmv_s_x_d, void, ptr, tl, env) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index c26a186d6a..7e1efeec05 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -556,6 +556,7 @@ vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r +vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2 vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 46651dfb10..7720ffecde 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2243,3 +2243,29 @@ static bool trans_vext_x_v(DisasContext *s, arg_r *a) } return false; } + +/* Integer Scalar Move Instruction */ +typedef void (* gen_helper_vmv_s_x)(TCGv_ptr, TCGv, TCGv_env); +static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) +{ + if (vext_check_isa_ill(s, RVV)) { + TCGv_ptr dest; + TCGv src1; + gen_helper_vmv_s_x fns[4] = { + gen_helper_vmv_s_x_b, gen_helper_vmv_s_x_h, + gen_helper_vmv_s_x_w, gen_helper_vmv_s_x_d + }; + + src1 = tcg_temp_new(); + dest = tcg_temp_new_ptr(); + gen_get_gpr(src1, a->rs1); + tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); + + fns[s->sew](dest, src1, cpu_env); + + tcg_temp_free(src1); + tcg_temp_free_ptr(dest); + return true; + } + return false; +} diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 8704ee120f..66ee69da99 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4460,3 +4460,18 @@ GEN_VEXT_X_V(vext_x_v_b, uint8_t, H1) GEN_VEXT_X_V(vext_x_v_h, uint16_t, H2) GEN_VEXT_X_V(vext_x_v_w, uint32_t, H4) GEN_VEXT_X_V(vext_x_v_d, uint64_t, H8) + +/* Integer Scalar Move Instruction */ +#define GEN_VEXT_VMV_S_X(NAME, ETYPE, H, CLEAR_FN) \ +void HELPER(NAME)(void *vd, target_ulong s1, CPURISCVState *env) \ +{ \ + if (env->vl == 0) { \ + return; \ + } \ + *((ETYPE *)vd + H(0)) = s1; \ + CLEAR_FN(vd, 1, sizeof(ETYPE), env_archcpu(env)->cfg.vlen / 8); \ +} +GEN_VEXT_VMV_S_X(vmv_s_x_b, uint8_t, H1, clearb) +GEN_VEXT_VMV_S_X(vmv_s_x_h, uint16_t, H2, clearh) +GEN_VEXT_VMV_S_X(vmv_s_x_w, uint32_t, H4, clearl) +GEN_VEXT_VMV_S_X(vmv_s_x_d, uint64_t, H8, clearq)