From patchwork Wed Mar 11 22:18:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Niek Linnenbank X-Patchwork-Id: 1253246 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=M65ECtSr; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48d5x160jnz9sQx for ; Thu, 12 Mar 2020 09:19:49 +1100 (AEDT) Received: from localhost ([::1]:58682 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jC9hb-0003gI-HK for incoming@patchwork.ozlabs.org; Wed, 11 Mar 2020 18:19:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59145) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jC9gz-0003cR-SU for qemu-devel@nongnu.org; Wed, 11 Mar 2020 18:19:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jC9gy-0004gA-Io for qemu-devel@nongnu.org; Wed, 11 Mar 2020 18:19:09 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:38557) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1jC9gy-0004ed-DB; Wed, 11 Mar 2020 18:19:08 -0400 Received: by mail-wm1-x343.google.com with SMTP id h83so472421wmf.3; Wed, 11 Mar 2020 15:19:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UIByMOMQQIv55mL19I+5dwrlTsd6XzXiE+TBLVFchfk=; b=M65ECtSr3LkZ1RWAeNkMQC4YuBpNqyasVxiGTDkd7zLDD/Jg3/N/fntJP5Z30nVEPI 5iaIok2YlRPI8GaRFpuWdKgxmu4QxIVW3c2MdJOqq+jTqWpbj5GdfwDUz/BT6IG8iw80 K7hDn+dCDyCDGNmFCx2CI6DW3aUW3hDcwQJQcfDI+a+9b4ZRjnpx7FHRyMoeN8lv8U8n Cf0zhoThaenyerE+BkXOtQD5aTIU2GQfNXphAfFS6EnF74dshmCvynM6Z+ICOhYdX6CU oqL4O6XIg0Qg8QFDAyWK4GG6iOBvDZ7lINGjNJ6hjINb1Qoq+B4H83L4cRmC1WEaB3u9 jstg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UIByMOMQQIv55mL19I+5dwrlTsd6XzXiE+TBLVFchfk=; b=MNAbkgYzbUb8qzSoGUG7z+/9INsWcjWY7FjEyOmELQj9jp9WdCj0AJ4lw8P7KGMaiz lXdD0yyGLrHd4zp2iXGNNi4/3LaLKTQ3J4IkXVFWGejoP79fgiAKvkQ1x47xYrpP3hOU sn6WNFCgLo36kvt78W8bB2jA1OmIH5ABWmeW8ch/cAPqKuu5vgpGxzwgIqgiMfWek1h7 qe8U9bacUYZrHZu1rlitxmzj8h3kAZTlmwyCSQ6A/PTEHgX6Nbbq++1lqbO/o8YDu1Ok G2pDT2HKY2QhbDv/rNuswqqWWGPS+JkoCxRpyyzVzeh1aAV48hovKzbP+hCVrBcqaUTI LoUw== X-Gm-Message-State: ANhLgQ1m8sdwMwryZV58aa9ASzsP8CMYBV42gwme+pa70gJzMHaoYa/Z KkEFOk/D36GlOc1fLKB7RAh+hnAM X-Google-Smtp-Source: ADFU+vuDYYD2IlSd1exv1bFVsktsk7IHHcfm4sQ1zkqP2xq+ybvkEzb46AoeTGqbzisDtU15GjXNsg== X-Received: by 2002:a1c:7419:: with SMTP id p25mr845950wmc.159.1583965147153; Wed, 11 Mar 2020 15:19:07 -0700 (PDT) Received: from pavilion.home ([2a02:a456:6be8:1:8edc:d4ff:fe8b:18b7]) by smtp.gmail.com with ESMTPSA id q7sm19346796wrd.54.2020.03.11.15.19.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2020 15:19:06 -0700 (PDT) From: Niek Linnenbank To: qemu-devel@nongnu.org Subject: [PATCH v8 04/18] hw/arm/allwinner-h3: add USB host controller Date: Wed, 11 Mar 2020 23:18:40 +0100 Message-Id: <20200311221854.30370-5-nieklinnenbank@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200311221854.30370-1-nieklinnenbank@gmail.com> References: <20200311221854.30370-1-nieklinnenbank@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, jasowang@redhat.com, b.galvani@gmail.com, Niek Linnenbank , qemu-arm@nongnu.org, imammedo@redhat.com, philmd@redhat.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The Allwinner H3 System on Chip contains multiple USB 2.0 bus connections which provide software access using the Enhanced Host Controller Interface (EHCI) and Open Host Controller Interface (OHCI) interfaces. This commit adds support for both interfaces in the Allwinner H3 System on Chip. Signed-off-by: Niek Linnenbank Reviewed-by: Gerd Hoffmann Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Tested-by: Philippe Mathieu-Daudé --- hw/usb/hcd-ehci.h | 1 + include/hw/arm/allwinner-h3.h | 8 +++++++ hw/arm/allwinner-h3.c | 44 +++++++++++++++++++++++++++++++++++ hw/usb/hcd-ehci-sysbus.c | 17 ++++++++++++++ hw/arm/Kconfig | 2 ++ 5 files changed, 72 insertions(+) diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h index 0298238f0b..edb59311c4 100644 --- a/hw/usb/hcd-ehci.h +++ b/hw/usb/hcd-ehci.h @@ -342,6 +342,7 @@ typedef struct EHCIPCIState { #define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb" #define TYPE_PLATFORM_EHCI "platform-ehci-usb" #define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb" +#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb" #define TYPE_TEGRA2_EHCI "tegra2-ehci-usb" #define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb" #define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb" diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index abdc20871a..4f4dcbcd17 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -56,6 +56,14 @@ enum { AW_H3_SRAM_A1, AW_H3_SRAM_A2, AW_H3_SRAM_C, + AW_H3_EHCI0, + AW_H3_OHCI0, + AW_H3_EHCI1, + AW_H3_OHCI1, + AW_H3_EHCI2, + AW_H3_OHCI2, + AW_H3_EHCI3, + AW_H3_OHCI3, AW_H3_CCU, AW_H3_PIT, AW_H3_UART0, diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index 1fff3c317b..c205f06738 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -28,6 +28,7 @@ #include "hw/sysbus.h" #include "hw/char/serial.h" #include "hw/misc/unimp.h" +#include "hw/usb/hcd-ehci.h" #include "sysemu/sysemu.h" #include "hw/arm/allwinner-h3.h" @@ -36,6 +37,14 @@ const hwaddr allwinner_h3_memmap[] = { [AW_H3_SRAM_A1] = 0x00000000, [AW_H3_SRAM_A2] = 0x00044000, [AW_H3_SRAM_C] = 0x00010000, + [AW_H3_EHCI0] = 0x01c1a000, + [AW_H3_OHCI0] = 0x01c1a400, + [AW_H3_EHCI1] = 0x01c1b000, + [AW_H3_OHCI1] = 0x01c1b400, + [AW_H3_EHCI2] = 0x01c1c000, + [AW_H3_OHCI2] = 0x01c1c400, + [AW_H3_EHCI3] = 0x01c1d000, + [AW_H3_OHCI3] = 0x01c1d400, [AW_H3_CCU] = 0x01c20000, [AW_H3_PIT] = 0x01c20c00, [AW_H3_UART0] = 0x01c28000, @@ -144,6 +153,14 @@ enum { AW_H3_GIC_SPI_UART3 = 3, AW_H3_GIC_SPI_TIMER0 = 18, AW_H3_GIC_SPI_TIMER1 = 19, + AW_H3_GIC_SPI_EHCI0 = 72, + AW_H3_GIC_SPI_OHCI0 = 73, + AW_H3_GIC_SPI_EHCI1 = 74, + AW_H3_GIC_SPI_OHCI1 = 75, + AW_H3_GIC_SPI_EHCI2 = 76, + AW_H3_GIC_SPI_OHCI2 = 77, + AW_H3_GIC_SPI_EHCI3 = 78, + AW_H3_GIC_SPI_OHCI3 = 79, }; /* Allwinner H3 general constants */ @@ -284,6 +301,33 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) qdev_init_nofail(DEVICE(&s->ccu)); sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]); + /* Universal Serial Bus */ + sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_EHCI0)); + sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI1], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_EHCI1)); + sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI2], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_EHCI2)); + sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI3], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_EHCI3)); + + sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI0], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_OHCI0)); + sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI1], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_OHCI1)); + sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI2], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_OHCI2)); + sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI3], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_OHCI3)); + /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2, qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0), diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c index 5b7991cffe..3730736540 100644 --- a/hw/usb/hcd-ehci-sysbus.c +++ b/hw/usb/hcd-ehci-sysbus.c @@ -131,6 +131,22 @@ static const TypeInfo ehci_exynos4210_type_info = { .class_init = ehci_exynos4210_class_init, }; +static void ehci_aw_h3_class_init(ObjectClass *oc, void *data) +{ + SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); + DeviceClass *dc = DEVICE_CLASS(oc); + + sec->capsbase = 0x0; + sec->opregbase = 0x10; + set_bit(DEVICE_CATEGORY_USB, dc->categories); +} + +static const TypeInfo ehci_aw_h3_type_info = { + .name = TYPE_AW_H3_EHCI, + .parent = TYPE_SYS_BUS_EHCI, + .class_init = ehci_aw_h3_class_init, +}; + static void ehci_tegra2_class_init(ObjectClass *oc, void *data) { SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); @@ -252,6 +268,7 @@ static void ehci_sysbus_register_types(void) type_register_static(&ehci_type_info); type_register_static(&ehci_platform_type_info); type_register_static(&ehci_exynos4210_type_info); + type_register_static(&ehci_aw_h3_type_info); type_register_static(&ehci_tegra2_type_info); type_register_static(&ehci_ppc4xx_type_info); type_register_static(&ehci_fusbh200_type_info); diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index fcdc651b73..f6422d5466 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -304,6 +304,8 @@ config ALLWINNER_H3 select ARM_TIMER select ARM_GIC select UNIMP + select USB_OHCI + select USB_EHCI_SYSBUS config RASPI bool