From patchwork Sun Mar 1 21:50:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Niek Linnenbank X-Patchwork-Id: 1247382 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=SQ+dymuj; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48Vxr860fZz9sSr for ; Mon, 2 Mar 2020 08:54:16 +1100 (AEDT) Received: from localhost ([::1]:52188 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j8WXO-0007Lf-Ou for incoming@patchwork.ozlabs.org; Sun, 01 Mar 2020 16:54:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57648) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j8WTy-00013N-8Q for qemu-devel@nongnu.org; Sun, 01 Mar 2020 16:50:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j8WTw-0006H2-S1 for qemu-devel@nongnu.org; Sun, 01 Mar 2020 16:50:42 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:41769) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j8WTw-0006F2-LT; Sun, 01 Mar 2020 16:50:40 -0500 Received: by mail-wr1-x443.google.com with SMTP id v4so10056472wrs.8; Sun, 01 Mar 2020 13:50:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=f9EeKoshn+W4ruJkmiJc8a12kPGrCM1oFv4DDEOMVFY=; b=SQ+dymujMwNz15LtZqZrkYuX1u5oXCy9u9v3mLam7I6MGlZvwEH+gx7ALhA+UpEct4 7QEYBOTnKrzgjIisUmlzvpZ8Gm+VG12QoAntO9LKbLlxlY0aq0nIU1aR4rM5bMo969xN etWAGciCg0osSGt+L9ehEYWcrzHD98tNUXQe2UveWf6sdkrgr9Dz3QQ1ZdSlVKy9sg4H I+F/ucviwRrKxJtSsDvrd+g4WDt3H/qhKxEsvHAfXjz4w1/c4DY0lSNbV3JtFD6XBFI6 l7BSgxYxQ0DSarIWHhIqs/Ql4XQWnpoGsHM0rGOfR2gzVl++8G22LTyGqpGNs1v+/ADU nb9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f9EeKoshn+W4ruJkmiJc8a12kPGrCM1oFv4DDEOMVFY=; b=q21jVxLqHVSxJkNXXclM4APTIQobAURpOJJOeWGZJgM1hAueyy6xc8mW2MucCy7ZXE MUP3H4L696Gt8curB7RJa1zixanmijSy7lLhPeAfcqjhZMB+2rX0TIhJme7gE8fIpqor FH2knPjU8AnCM1RK7/JQFW6H3zR8IUt0bADb2TKILelrgUGsZSFdSK8q5UZUeHved3IG ganCkQPmgGqfFXr+54bvDn4+sWi7nvGjDfcb2wJR3yZ6uFO8X0cWZgd+keOmNda9kjMP c8OJS61ee9qHVT6Xn2lamtEWMx+B9lhECrgvmK6wQMj8SCjS/HX5oG/GtLC7kyvRGJ2a m9+A== X-Gm-Message-State: APjAAAVUIM0CYo8m+gNOu7f0RpZoJiIHdZgMruMvdHB/CSHDvYq8KheS EfgI4vTCjzN4v6xNgxDQ4k3iq4Ha X-Google-Smtp-Source: APXvYqz/CYniTP7iKpYZ4IdDTdcSn34eXhAh8Ik7Xk8xdWo5TbJlOZ66ryJOg74I2NxGSv3HwOaJ2w== X-Received: by 2002:a05:6000:10c5:: with SMTP id b5mr13297651wrx.203.1583099439312; Sun, 01 Mar 2020 13:50:39 -0800 (PST) Received: from pavilion.home ([2a02:a456:6be8:1:8edc:d4ff:fe8b:18b7]) by smtp.gmail.com with ESMTPSA id e8sm25033124wrr.69.2020.03.01.13.50.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Mar 2020 13:50:38 -0800 (PST) From: Niek Linnenbank To: qemu-devel@nongnu.org Subject: [PATCH v6 04/18] hw/arm/allwinner-h3: add USB host controller Date: Sun, 1 Mar 2020 22:50:15 +0100 Message-Id: <20200301215029.15196-5-nieklinnenbank@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200301215029.15196-1-nieklinnenbank@gmail.com> References: <20200301215029.15196-1-nieklinnenbank@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, jasowang@redhat.com, b.galvani@gmail.com, Niek Linnenbank , qemu-arm@nongnu.org, imammedo@redhat.com, philmd@redhat.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The Allwinner H3 System on Chip contains multiple USB 2.0 bus connections which provide software access using the Enhanced Host Controller Interface (EHCI) and Open Host Controller Interface (OHCI) interfaces. This commit adds support for both interfaces in the Allwinner H3 System on Chip. Signed-off-by: Niek Linnenbank Reviewed-by: Gerd Hoffmann Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée --- hw/usb/hcd-ehci.h | 1 + include/hw/arm/allwinner-h3.h | 8 +++++++ hw/arm/allwinner-h3.c | 44 +++++++++++++++++++++++++++++++++++ hw/usb/hcd-ehci-sysbus.c | 17 ++++++++++++++ hw/arm/Kconfig | 2 ++ 5 files changed, 72 insertions(+) diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h index 0298238f0b..edb59311c4 100644 --- a/hw/usb/hcd-ehci.h +++ b/hw/usb/hcd-ehci.h @@ -342,6 +342,7 @@ typedef struct EHCIPCIState { #define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb" #define TYPE_PLATFORM_EHCI "platform-ehci-usb" #define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb" +#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb" #define TYPE_TEGRA2_EHCI "tegra2-ehci-usb" #define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb" #define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb" diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index abdc20871a..4f4dcbcd17 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -56,6 +56,14 @@ enum { AW_H3_SRAM_A1, AW_H3_SRAM_A2, AW_H3_SRAM_C, + AW_H3_EHCI0, + AW_H3_OHCI0, + AW_H3_EHCI1, + AW_H3_OHCI1, + AW_H3_EHCI2, + AW_H3_OHCI2, + AW_H3_EHCI3, + AW_H3_OHCI3, AW_H3_CCU, AW_H3_PIT, AW_H3_UART0, diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index 1fff3c317b..c205f06738 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -28,6 +28,7 @@ #include "hw/sysbus.h" #include "hw/char/serial.h" #include "hw/misc/unimp.h" +#include "hw/usb/hcd-ehci.h" #include "sysemu/sysemu.h" #include "hw/arm/allwinner-h3.h" @@ -36,6 +37,14 @@ const hwaddr allwinner_h3_memmap[] = { [AW_H3_SRAM_A1] = 0x00000000, [AW_H3_SRAM_A2] = 0x00044000, [AW_H3_SRAM_C] = 0x00010000, + [AW_H3_EHCI0] = 0x01c1a000, + [AW_H3_OHCI0] = 0x01c1a400, + [AW_H3_EHCI1] = 0x01c1b000, + [AW_H3_OHCI1] = 0x01c1b400, + [AW_H3_EHCI2] = 0x01c1c000, + [AW_H3_OHCI2] = 0x01c1c400, + [AW_H3_EHCI3] = 0x01c1d000, + [AW_H3_OHCI3] = 0x01c1d400, [AW_H3_CCU] = 0x01c20000, [AW_H3_PIT] = 0x01c20c00, [AW_H3_UART0] = 0x01c28000, @@ -144,6 +153,14 @@ enum { AW_H3_GIC_SPI_UART3 = 3, AW_H3_GIC_SPI_TIMER0 = 18, AW_H3_GIC_SPI_TIMER1 = 19, + AW_H3_GIC_SPI_EHCI0 = 72, + AW_H3_GIC_SPI_OHCI0 = 73, + AW_H3_GIC_SPI_EHCI1 = 74, + AW_H3_GIC_SPI_OHCI1 = 75, + AW_H3_GIC_SPI_EHCI2 = 76, + AW_H3_GIC_SPI_OHCI2 = 77, + AW_H3_GIC_SPI_EHCI3 = 78, + AW_H3_GIC_SPI_OHCI3 = 79, }; /* Allwinner H3 general constants */ @@ -284,6 +301,33 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) qdev_init_nofail(DEVICE(&s->ccu)); sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]); + /* Universal Serial Bus */ + sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_EHCI0)); + sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI1], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_EHCI1)); + sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI2], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_EHCI2)); + sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI3], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_EHCI3)); + + sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI0], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_OHCI0)); + sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI1], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_OHCI1)); + sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI2], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_OHCI2)); + sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI3], + qdev_get_gpio_in(DEVICE(&s->gic), + AW_H3_GIC_SPI_OHCI3)); + /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2, qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0), diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c index 5b7991cffe..3730736540 100644 --- a/hw/usb/hcd-ehci-sysbus.c +++ b/hw/usb/hcd-ehci-sysbus.c @@ -131,6 +131,22 @@ static const TypeInfo ehci_exynos4210_type_info = { .class_init = ehci_exynos4210_class_init, }; +static void ehci_aw_h3_class_init(ObjectClass *oc, void *data) +{ + SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); + DeviceClass *dc = DEVICE_CLASS(oc); + + sec->capsbase = 0x0; + sec->opregbase = 0x10; + set_bit(DEVICE_CATEGORY_USB, dc->categories); +} + +static const TypeInfo ehci_aw_h3_type_info = { + .name = TYPE_AW_H3_EHCI, + .parent = TYPE_SYS_BUS_EHCI, + .class_init = ehci_aw_h3_class_init, +}; + static void ehci_tegra2_class_init(ObjectClass *oc, void *data) { SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); @@ -252,6 +268,7 @@ static void ehci_sysbus_register_types(void) type_register_static(&ehci_type_info); type_register_static(&ehci_platform_type_info); type_register_static(&ehci_exynos4210_type_info); + type_register_static(&ehci_aw_h3_type_info); type_register_static(&ehci_tegra2_type_info); type_register_static(&ehci_ppc4xx_type_info); type_register_static(&ehci_fusbh200_type_info); diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index a7034218f0..5d78deba11 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -303,6 +303,8 @@ config ALLWINNER_H3 select ARM_TIMER select ARM_GIC select UNIMP + select USB_OHCI + select USB_EHCI_SYSBUS config RASPI bool