From patchwork Sat May 25 22:50:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 1105441 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=vivier.eu Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45BJx15y12z9s4V for ; Sun, 26 May 2019 09:15:01 +1000 (AEST) Received: from localhost ([127.0.0.1]:47490 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUfsR-0004Xp-LR for incoming@patchwork.ozlabs.org; Sat, 25 May 2019 19:14:59 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34219) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUflD-0006f1-HL for qemu-devel@nongnu.org; Sat, 25 May 2019 19:07:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hUfVD-0002YM-I7 for qemu-devel@nongnu.org; Sat, 25 May 2019 18:51:01 -0400 Received: from mout.kundenserver.de ([212.227.17.24]:49447) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hUfV6-0002Nl-Ih; Sat, 25 May 2019 18:50:52 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue106 [212.227.15.183]) with ESMTPSA (Nemesis) id 1MwgKC-1ggRFs1DVi-00y7UD; Sun, 26 May 2019 00:50:22 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Sun, 26 May 2019 00:50:04 +0200 Message-Id: <20190525225013.13916-2-laurent@vivier.eu> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190525225013.13916-1-laurent@vivier.eu> References: <20190525225013.13916-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:gdgqlnd/RVlkWCviSEo0FWZtirTvv0+CDYd/USC4nCAQhkhJPEm 6ZF8Fx0FcyYFmCErOiTBaX8oTm5I9NbbAf7kvWthODatguj1KqbdbbKLNaI9D3jwjGwcmwk Kvw8qkPQrG6k1aeykxCAYQNDMrSXeAdzG215oku2leaadb34uvdielN3M+wKcytYHmPoXVG 1ZaHHIirPS+Wu+7iAwETA== X-UI-Out-Filterresults: notjunk:1; V03:K0:gVZbSFfgSAA=:IffxhrUjD8JGF7wfE0oPIt jqWX3nGGBCpHCcPfkLD/UVmTu4ugrcCPlVyFDAL7RLk18tVjyda46ICheid6eBwpPuDQZ5CEz MtXFKUbVgn/kf7f6dV0myz0C8ZTUcK1prcoyZObQJY7IpBMJSScA0QxGB1aWYszw1M6VRLQmB LNsWnLFg2BbR+a71Ylm7W7MPFEKfnPdACQevQF+qUnzCLx0Z/Sc/RrfhQ4SlmSHb7JgBWtcWy ZUjrX5BU4EKEiKB+XP4CkzcfNbzFSJaWN2F0nf0d5tSM2oQVmfYbMKX/8lsY4KclHqHir7f5c wxgS1Ro2M06uH8nXIl6Ywn8Vcog9kV45NihIeDACYQqBZ+CAWzaMQX7mZI2aO/j2Xhks+6k17 IntrSzKd2UlSBGE/QnsEl/u3D1FxedbqmC7oxJAIxz3iM6JxtuI6yr3v56utLjaVxGPok3ZUb zJXzCBpg+WNjpmdRip5kfJCFDxd1GyOckHBiLJ08vRUYLRj0JxzX6krB1B12ePfzPRUemxkLX 2f6NiCDMFsALMGbWKYg562A0CTtle1qZfQhwRhQ8qvi1dU9UA1C2swv5JxVw2eGnCMe13O241 dBvB4DG9aSekkSxTQIPIH4xJTieJDoJLuWQDYyQsTem2V25ICEwC8yEtJK7vhzny8RAER9gvi zZ94yYc/n4v70/D1Bck41fxUXLTcXS8rd+QuRzA/VjiaUGWjRe1qwNVKwVUJZ1aHAcrzcQeEO fPXy/ag0arL49ARKZH5Ly6BUzu72MQePW24eBN/yFQv7Njr5aP8vXJsvHs4= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.17.24 Subject: [Qemu-devel] [PATCH v7 01/10] escc: introduce a selector for the register bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , "Dr . David Alan Gilbert" , qemu-block@nongnu.org, Thomas Huth , Jason Wang , Mark Cave-Ayland , Laurent Vivier , Max Reitz , =?utf-8?q?Herv=C3=A9_Poussineau?= , Gerd Hoffmann , Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" On Sparc and PowerMac, the bit 0 of the address selects the register type (control or data) and bit 1 selects the channel (B or A). On m68k Macintosh, the bit 0 selects the channel and bit 1 the register type. This patch introduces a new parameter (bit_swap) to the device interface to indicate bits usage must be swapped between registers and channels. For the moment all the machines use the bit 0, but this change will be needed to emulate Quadra 800. Signed-off-by: Laurent Vivier Reviewed-by: Hervé Poussineau Reviewed-by: Thomas Huth --- hw/char/escc.c | 30 ++++++++++++++++++++++++------ include/hw/char/escc.h | 1 + 2 files changed, 25 insertions(+), 6 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index c5b05a63f1..3eee2e66e8 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -42,14 +42,21 @@ * mouse and keyboard ports don't implement all functions and they are * only asynchronous. There is no DMA. * - * Z85C30 is also used on PowerMacs. There are some small differences - * between Sparc version (sunzilog) and PowerMac (pmac): + * Z85C30 is also used on PowerMacs and m68k Macs. + * + * There are some small differences between Sparc version (sunzilog) + * and PowerMac (pmac): * Offset between control and data registers * There is some kind of lockup bug, but we can ignore it * CTS is inverted * DMA on pmac using DBDMA chip * pmac can do IRDA and faster rates, sunzilog can only do 38400 * pmac baud rate generator clock is 3.6864 MHz, sunzilog 4.9152 MHz + * + * Linux driver for m68k Macs is the same as for PowerMac (pmac_zilog), + * but registers are grouped by type and not by channel: + * channel is selected by bit 0 of the address (instead of bit 1) + * and register is selected by bit 1 of the address (instead of bit 0). */ /* @@ -169,6 +176,16 @@ static void handle_kbd_command(ESCCChannelState *s, int val); static int serial_can_receive(void *opaque); static void serial_receive_byte(ESCCChannelState *s, int ch); +static int reg_shift(ESCCState *s) +{ + return s->bit_swap ? s->it_shift + 1 : s->it_shift; +} + +static int chn_shift(ESCCState *s) +{ + return s->bit_swap ? s->it_shift : s->it_shift + 1; +} + static void clear_queue(void *opaque) { ESCCChannelState *s = opaque; @@ -433,8 +450,8 @@ static void escc_mem_write(void *opaque, hwaddr addr, int newreg, channel; val &= 0xff; - saddr = (addr >> serial->it_shift) & 1; - channel = (addr >> (serial->it_shift + 1)) & 1; + saddr = (addr >> reg_shift(serial)) & 1; + channel = (addr >> chn_shift(serial)) & 1; s = &serial->chn[channel]; switch (saddr) { case SERIAL_CTRL: @@ -544,8 +561,8 @@ static uint64_t escc_mem_read(void *opaque, hwaddr addr, uint32_t ret; int channel; - saddr = (addr >> serial->it_shift) & 1; - channel = (addr >> (serial->it_shift + 1)) & 1; + saddr = (addr >> reg_shift(serial)) & 1; + channel = (addr >> chn_shift(serial)) & 1; s = &serial->chn[channel]; switch (saddr) { case SERIAL_CTRL: @@ -829,6 +846,7 @@ static void escc_realize(DeviceState *dev, Error **errp) static Property escc_properties[] = { DEFINE_PROP_UINT32("frequency", ESCCState, frequency, 0), DEFINE_PROP_UINT32("it_shift", ESCCState, it_shift, 0), + DEFINE_PROP_BOOL("bit_swap", ESCCState, bit_swap, false), DEFINE_PROP_UINT32("disabled", ESCCState, disabled, 0), DEFINE_PROP_UINT32("chnBtype", ESCCState, chn[0].type, 0), DEFINE_PROP_UINT32("chnAtype", ESCCState, chn[1].type, 0), diff --git a/include/hw/char/escc.h b/include/hw/char/escc.h index 42aca83611..8762f61c14 100644 --- a/include/hw/char/escc.h +++ b/include/hw/char/escc.h @@ -50,6 +50,7 @@ typedef struct ESCCState { struct ESCCChannelState chn[2]; uint32_t it_shift; + bool bit_swap; MemoryRegion mmio; uint32_t disabled; uint32_t frequency;