From patchwork Wed May 22 14:29:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 1103372 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 458FVh10RGz9s5c for ; Thu, 23 May 2019 00:33:32 +1000 (AEST) Received: from localhost ([127.0.0.1]:44338 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hTSJ7-0002M9-VI for incoming@patchwork.ozlabs.org; Wed, 22 May 2019 10:33:30 -0400 Received: from eggs.gnu.org ([209.51.188.92]:53384) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hTSG1-00005d-Mx for qemu-devel@nongnu.org; Wed, 22 May 2019 10:30:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hTSFz-0007So-Io for qemu-devel@nongnu.org; Wed, 22 May 2019 10:30:17 -0400 Received: from mail03.asahi-net.or.jp ([202.224.55.15]:35405) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hTSFz-00076e-7v for qemu-devel@nongnu.org; Wed, 22 May 2019 10:30:15 -0400 Received: from h61-195-96-97.vps.ablenet.jp (h61-195-96-97.ablenetvps.ne.jp [61.195.96.97]) (Authenticated sender: PQ4Y-STU) by mail03.asahi-net.or.jp (Postfix) with ESMTPA id EF92E429AB; Wed, 22 May 2019 23:30:05 +0900 (JST) Received: from yo-satoh-debian.localdomain (v045049.dynamic.ppp.asahi-net.or.jp [124.155.45.49]) by h61-195-96-97.vps.ablenet.jp (Postfix) with ESMTPSA id A801B240087; Wed, 22 May 2019 23:30:04 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Date: Wed, 22 May 2019 23:29:46 +0900 Message-Id: <20190522142956.41916-3-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190522142956.41916-1-ysato@users.sourceforge.jp> References: <20190522142956.41916-1-ysato@users.sourceforge.jp> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 202.224.55.15 Subject: [Qemu-devel] [PATCH v15 02/12] hw/registerfields.h: Add 8bit and 16bit register macros. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, Yoshinori Sato , philmd@redhat.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Some RX peripheral using 8bit and 16bit registers. Added 8bit and 16bit APIs. Signed-off-by: Yoshinori Sato --- include/hw/registerfields.h | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h index 2659a58737..8573bdd7db 100644 --- a/include/hw/registerfields.h +++ b/include/hw/registerfields.h @@ -13,11 +13,17 @@ #include "qemu/bitops.h" -/* Define constants for a 32 bit register */ +/* Define constants for a 8, 16 and 32 bit register */ /* This macro will define A_FOO, for the byte address of a register * as well as R_FOO for the uint32_t[] register number (A_FOO / 4). */ +#define REG8(reg, addr) \ + enum { A_ ## reg = (addr) }; \ + enum { R_ ## reg = (addr) }; +#define REG16(reg, addr) \ + enum { A_ ## reg = (addr) }; \ + enum { R_ ## reg = (addr) / 2 }; #define REG32(reg, addr) \ enum { A_ ## reg = (addr) }; \ enum { R_ ## reg = (addr) / 4 }; @@ -34,6 +40,12 @@ MAKE_64BIT_MASK(shift, length)}; /* Extract a field from a register */ +#define FIELD_EX8(storage, reg, field) \ + extract8((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) +#define FIELD_EX16(storage, reg, field) \ + extract16((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) #define FIELD_EX32(storage, reg, field) \ extract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ R_ ## reg ## _ ## field ## _LENGTH) @@ -49,6 +61,22 @@ * Assigning values larger then the target field will result in * compilation warnings. */ +#define FIELD_DP8(storage, reg, field, val) ({ \ + struct { \ + unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ + } v = { .v = val }; \ + uint8_t d; \ + d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH, v.v); \ + d; }) +#define FIELD_DP16(storage, reg, field, val) ({ \ + struct { \ + unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ + } v = { .v = val }; \ + uint16_t d; \ + d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH, v.v); \ + d; }) #define FIELD_DP32(storage, reg, field, val) ({ \ struct { \ unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \