From patchwork Mon Mar 4 02:00:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 1050992 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.intel.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44CPRz0g7Rz9s5R for ; Mon, 4 Mar 2019 13:41:51 +1100 (AEDT) Received: from localhost ([127.0.0.1]:47161 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0dY4-00016u-To for incoming@patchwork.ozlabs.org; Sun, 03 Mar 2019 21:41:48 -0500 Received: from eggs.gnu.org ([209.51.188.92]:56421) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0d5A-0004ru-V9 for qemu-devel@nongnu.org; Sun, 03 Mar 2019 21:11:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h0d59-0001hf-TF for qemu-devel@nongnu.org; Sun, 03 Mar 2019 21:11:56 -0500 Received: from mga18.intel.com ([134.134.136.126]:8723) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h0d59-0001hK-JU for qemu-devel@nongnu.org; Sun, 03 Mar 2019 21:11:55 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Mar 2019 18:11:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,438,1544515200"; d="scan'208";a="128737547" Received: from xy-skl-4s.sh.intel.com ([10.239.48.75]) by fmsmga008.fm.intel.com with ESMTP; 03 Mar 2019 18:11:50 -0800 From: Xiaoyao Li To: Date: Mon, 4 Mar 2019 10:00:42 +0800 Message-Id: <20190304020042.211830-1-xiaoyao.li@linux.intel.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.126 X-Mailman-Approved-At: Sun, 03 Mar 2019 21:40:51 -0500 Subject: [Qemu-devel] [PATCH] x86: define a new MSR based feature word -- FEAT_CORE_CAPABILITY X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , kvm@vger.kernel.org, Marcelo Tosatti , qemu-devel@nongnu.org, Paolo Bonzini , Xiaoyao Li , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" MSR IA32_CORE_CAPABILITY is a feature-enumerating MSR, which enumerates the capabilitiy of enabling detection of split locks (bit 5 of MSR_TEST_CTL). MSR IA32_CORE_CAPABILITY can be enumerated by CPUID.0X7.0:EDX[30]. Related kernel patches can be found here: https://lkml.org/lkml/2019/3/1/749 Patches 15-17 of kvm are exposing this feature to guest. If host has split lock detection feature, we can expose it to guest by using '-cpu host' with this patch and kernel's patches. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 22 +++++++++++++++++++++- target/i386/cpu.h | 3 +++ target/i386/kvm.c | 9 +++++++++ 3 files changed, 33 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d3aa6a815b..32df1d358a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1081,7 +1081,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "spec-ctrl", "stibp", - NULL, "arch-capabilities", NULL, "ssbd", + NULL, "arch-capabilities", "core-capability", "ssbd", }, .cpuid = { .eax = 7, @@ -1200,6 +1200,26 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { } }, }, + [FEAT_CORE_CAPABILITY] = { + .type = MSR_FEATURE_WORD, + .feat_names = { + NULL, NULL, NULL, NULL, + NULL, "split-lock-detect", NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .msr = { + .index = MSR_IA32_CORE_CAPABILITY, + .cpuid_dep = { + FEAT_7_0_EDX, + CPUID_7_0_EDX_CORE_CAPABILITY + }, + }, + }, }; typedef struct X86RegisterInfo32 { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 95112b9118..6eb89ac735 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -355,6 +355,7 @@ typedef enum X86Seg { #define MSR_IA32_SPEC_CTRL 0x48 #define MSR_VIRT_SSBD 0xc001011f #define MSR_IA32_PRED_CMD 0x49 +#define MSR_IA32_CORE_CAPABILITY 0xcf #define MSR_IA32_ARCH_CAPABILITIES 0x10a #define MSR_IA32_TSCDEADLINE 0x6e0 @@ -505,6 +506,7 @@ typedef enum FeatureWord { FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ FEAT_ARCH_CAPABILITIES, + FEAT_CORE_CAPABILITY, FEATURE_WORDS, } FeatureWord; @@ -696,6 +698,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/ +#define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) /*Core Capabilities*/ #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and diff --git a/target/i386/kvm.c b/target/i386/kvm.c index beae1b99da..8aafd1db77 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -96,6 +96,7 @@ static bool has_msr_spec_ctrl; static bool has_msr_virt_ssbd; static bool has_msr_smi_count; static bool has_msr_arch_capabs; +static bool has_msr_core_capabs; static uint32_t has_architectural_pmu_version; static uint32_t num_architectural_pmu_gp_counters; @@ -1507,6 +1508,9 @@ static int kvm_get_supported_msrs(KVMState *s) case MSR_IA32_ARCH_CAPABILITIES: has_msr_arch_capabs = true; break; + case MSR_IA32_CORE_CAPABILITY: + has_msr_core_capabs = true; + break; } } } @@ -2033,6 +2037,11 @@ static int kvm_put_msrs(X86CPU *cpu, int level) env->features[FEAT_ARCH_CAPABILITIES]); } + if (has_msr_core_capabs) { + kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY, + env->features[FEAT_CORE_CAPABILITY]); + } + /* * The following MSRs have side effects on the guest or are too heavy * for normal writeback. Limit them to reset or full state updates.