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[v9,07/14] target/arm: Define FIELDs for ID_DFR0

Message ID 20181205134243.4791-8-aaron@os.amperecomputing.com
State New
Headers show
Series More fully implement ARM PMUv3 | expand

Commit Message

Aaron Lindsay Dec. 5, 2018, 1:43 p.m. UTC
This is immediately necessary for the PMUv3 implementation to check
ID_DFR0.PerfMon to enable/disable specific features, but defines the
full complement of fields for possible future use elsewhere.

Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
---
 target/arm/cpu.h | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Peter Maydell Dec. 6, 2018, 3:56 p.m. UTC | #1
On Wed, 5 Dec 2018 at 13:43, Aaron Lindsay <aaron@os.amperecomputing.com> wrote:
>
> This is immediately necessary for the PMUv3 implementation to check
> ID_DFR0.PerfMon to enable/disable specific features, but defines the
> full complement of fields for possible future use elsewhere.
>
> Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
> ---
>  target/arm/cpu.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 627e5c1995..304e6e47b3 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1586,6 +1586,14 @@ FIELD(ID_AA64PFR0, GIC, 24, 4)
>  FIELD(ID_AA64PFR0, RAS, 28, 4)
>  FIELD(ID_AA64PFR0, SVE, 32, 4)
>
> +FIELD(ID_DFR0, COPDBG, 0, 4)
> +FIELD(ID_DFR0, COPSDBG, 4, 4)
> +FIELD(ID_DFR0, MMAPDBG, 8, 4)
> +FIELD(ID_DFR0, COPTRC, 12, 4)
> +FIELD(ID_DFR0, MMAPTRC, 16, 4)
> +FIELD(ID_DFR0, MPROFDBG, 20, 4)
> +FIELD(ID_DFR0, PERFMON, 24, 4)

Also
FIELD(ID_DFR0, TRACEFILT, 28, 4)

(this is a v8.4 field; we might as well add it since you
have another minor tweak that needs a respin.)

Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM
diff mbox series

Patch

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 627e5c1995..304e6e47b3 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1586,6 +1586,14 @@  FIELD(ID_AA64PFR0, GIC, 24, 4)
 FIELD(ID_AA64PFR0, RAS, 28, 4)
 FIELD(ID_AA64PFR0, SVE, 32, 4)
 
+FIELD(ID_DFR0, COPDBG, 0, 4)
+FIELD(ID_DFR0, COPSDBG, 4, 4)
+FIELD(ID_DFR0, MMAPDBG, 8, 4)
+FIELD(ID_DFR0, COPTRC, 12, 4)
+FIELD(ID_DFR0, MMAPTRC, 16, 4)
+FIELD(ID_DFR0, MPROFDBG, 20, 4)
+FIELD(ID_DFR0, PERFMON, 24, 4)
+
 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
 
 /* If adding a feature bit which corresponds to a Linux ELF