From patchwork Wed Jun 27 23:29:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 935786 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=vivier.eu Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41GK1847Hdz9rx7 for ; Thu, 28 Jun 2018 09:31:24 +1000 (AEST) Received: from localhost ([::1]:33615 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYJuE-0007yM-1s for incoming@patchwork.ozlabs.org; Wed, 27 Jun 2018 19:31:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48477) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYJtM-0007u3-Ai for qemu-devel@nongnu.org; Wed, 27 Jun 2018 19:30:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYJtK-0003iW-Uw for qemu-devel@nongnu.org; Wed, 27 Jun 2018 19:30:28 -0400 Received: from mout.kundenserver.de ([212.227.126.135]:37834) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYJtD-0003db-8b; Wed, 27 Jun 2018 19:30:19 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue001 [212.227.15.167]) with ESMTPSA (Nemesis) id 0MOXED-1fT4YO1a2H-005mgx; Thu, 28 Jun 2018 01:30:01 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 28 Jun 2018 01:29:44 +0200 Message-Id: <20180627232951.14725-4-laurent@vivier.eu> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180627232951.14725-1-laurent@vivier.eu> References: <20180627232951.14725-1-laurent@vivier.eu> X-Provags-ID: V03:K1:OtgBMjp5HVGwqOu6iC6fMfp7q6AVa0x55tME4kJnDp5ADhBemqc CyIResYThVfsE71QklnkEgCZ6NlTbr9ngCKCDgROLfS2tebt4EQInIlBcK+5YWGFfP+/MwM rtB7JEuluq+oAETg+UTRq7tJPpt+z4NutymsO9dxVdVQM6pqtLgKFRG/Rk5XSJGHmbqC+xN 81h4xc/VBKc8ySg2wd29g== X-UI-Out-Filterresults: notjunk:1; V01:K0:Uin2GxQLHdk=:T77+v1nrq53u/2tPAPUBpo 483e1NkW9ynuP3g/ZxPTaMTkI/00y3oZxYQdEP/+QYOlXObXbyM3g7qBkOb/dERY/t0hxD5Ag GXHOhcCNpbBOK/A4gu0KTRSqGFqgZlWq4HfxZfUMc/ay0Z0la5zyzAgES3U/kr+ZaCXEiYO3J 39W5amzW8wa7divzy1TmNXSa30oIwuE/F0bifSwmf54JFYb7RRnXicms8LKat1jQLL24nZGhz ib7Y5wPKOhwmCdolVBlQqcTGlgwD23vw0f/mr2zphWi/vgBMMJi3dpRu8j9G5Dt7lalCPiDnv vq13rTeVnFTLyDkirDWvZR79hJElTcaOVplFjWn/qar5qMOehAllenYQ41WaHNKkdHrqjYRQD lXhedRxedHsyTMupzM1NAFGmxEhf1uNHQAoTA1WUPcUsjcZI2UIWvY3Lc+czUcWcLezVBtWls Jpb7V77/CISD97s+GevsMHnQdPv6VgRX6CRoepmYprrwIkRtQFVbozZmJNhVQCogsQKTri9J6 NqaM68jWNisqpxsW3ujYfvRMyG5x82z15chM4XDJ7GEnV/tAkQyVW++Wy372XS9jqVGvCdl/m tUQ1kYGSSkK2vL++6yBmMHFUAVrjxKo4Z/c7afiGApQIV6rARriO00eMQTrojzLKsLXYd5Xiz RXzY13rC3xv2vBo+QTh4cdy7QJz4UlFOTVNwGXvOQG1bf2g+zEMLiO/2kSixudn7dLHo= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.135 Subject: [Qemu-devel] [RFC v3 03/10] escc: introduce a selector for the register bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Jason Wang , Mark Cave-Ayland , "Dr. David Alan Gilbert" , Laurent Vivier , =?utf-8?q?Herv=C3=A9_Poussineau?= , Gerd Hoffmann , Paolo Bonzini , Max Reitz , Yongbok Kim , =?utf-8?q?Andreas_F=C3=A4rber?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" On Sparc and PowerMac, the bit 0 of the address selects the register type (control or data) and bit 1 selects the channel (B or A). On m68k Macintosh, the bit 0 selects the channel and bit 1 the register type. This patch introduces a new parameter (bit_swap) to the device interface to indicate bits usage must be swapped between registers and channels. For the moment all the machines use the bit 0, but this change will be needed to emulate Quadra 800. Signed-off-by: Laurent Vivier --- hw/char/escc.c | 30 ++++++++++++++++++++++++------ include/hw/char/escc.h | 1 + 2 files changed, 25 insertions(+), 6 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index 628f5f81f7..cec75b06f9 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -42,14 +42,21 @@ * mouse and keyboard ports don't implement all functions and they are * only asynchronous. There is no DMA. * - * Z85C30 is also used on PowerMacs. There are some small differences - * between Sparc version (sunzilog) and PowerMac (pmac): + * Z85C30 is also used on PowerMacs and m68k Macs. + * + * There are some small differences between Sparc version (sunzilog) + * and PowerMac (pmac): * Offset between control and data registers * There is some kind of lockup bug, but we can ignore it * CTS is inverted * DMA on pmac using DBDMA chip * pmac can do IRDA and faster rates, sunzilog can only do 38400 * pmac baud rate generator clock is 3.6864 MHz, sunzilog 4.9152 MHz + * + * Linux driver for m68k Macs is the same as for PowerMac (pmac_zilog), + * but registers are grouped by type and not by channel: + * channel is selected by bit 0 of the address (instead of bit 1) + * and register is selected by bit 1 of the address (instead of bit 0). */ /* @@ -169,6 +176,16 @@ static void handle_kbd_command(ESCCChannelState *s, int val); static int serial_can_receive(void *opaque); static void serial_receive_byte(ESCCChannelState *s, int ch); +static int reg_shift(ESCCState *s) +{ + return s->bit_swap ? s->it_shift + 1 : s->it_shift; +} + +static int chn_shift(ESCCState *s) +{ + return s->bit_swap ? s->it_shift : s->it_shift + 1; +} + static void clear_queue(void *opaque) { ESCCChannelState *s = opaque; @@ -433,8 +450,8 @@ static void escc_mem_write(void *opaque, hwaddr addr, int newreg, channel; val &= 0xff; - saddr = (addr >> serial->it_shift) & 1; - channel = (addr >> (serial->it_shift + 1)) & 1; + saddr = (addr >> reg_shift(serial)) & 1; + channel = (addr >> chn_shift(serial)) & 1; s = &serial->chn[channel]; switch (saddr) { case SERIAL_CTRL: @@ -537,8 +554,8 @@ static uint64_t escc_mem_read(void *opaque, hwaddr addr, uint32_t ret; int channel; - saddr = (addr >> serial->it_shift) & 1; - channel = (addr >> (serial->it_shift + 1)) & 1; + saddr = (addr >> reg_shift(serial)) & 1; + channel = (addr >> chn_shift(serial)) & 1; s = &serial->chn[channel]; switch (saddr) { case SERIAL_CTRL: @@ -822,6 +839,7 @@ static void escc_realize(DeviceState *dev, Error **errp) static Property escc_properties[] = { DEFINE_PROP_UINT32("frequency", ESCCState, frequency, 0), DEFINE_PROP_UINT32("it_shift", ESCCState, it_shift, 0), + DEFINE_PROP_BOOL("bit_swap", ESCCState, bit_swap, false), DEFINE_PROP_UINT32("disabled", ESCCState, disabled, 0), DEFINE_PROP_UINT32("chnBtype", ESCCState, chn[0].type, 0), DEFINE_PROP_UINT32("chnAtype", ESCCState, chn[1].type, 0), diff --git a/include/hw/char/escc.h b/include/hw/char/escc.h index 42aca83611..8762f61c14 100644 --- a/include/hw/char/escc.h +++ b/include/hw/char/escc.h @@ -50,6 +50,7 @@ typedef struct ESCCState { struct ESCCChannelState chn[2]; uint32_t it_shift; + bool bit_swap; MemoryRegion mmio; uint32_t disabled; uint32_t frequency;