From patchwork Wed Jun 27 23:23:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 935779 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=vivier.eu Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41GJtJ201yz9s01 for ; Thu, 28 Jun 2018 09:25:28 +1000 (AEST) Received: from localhost ([::1]:33574 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYJoT-0003HM-OT for incoming@patchwork.ozlabs.org; Wed, 27 Jun 2018 19:25:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46997) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYJnT-0002tR-AT for qemu-devel@nongnu.org; Wed, 27 Jun 2018 19:24:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYJnS-0007NH-61 for qemu-devel@nongnu.org; Wed, 27 Jun 2018 19:24:23 -0400 Received: from mout.kundenserver.de ([212.227.17.13]:58707) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYJnM-0007EX-Qi; Wed, 27 Jun 2018 19:24:17 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue105 [212.227.15.183]) with ESMTPSA (Nemesis) id 0MSr7l-1fgOQY2QOz-00RsYQ; Thu, 28 Jun 2018 01:23:55 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 28 Jun 2018 01:23:27 +0200 Message-Id: <20180627232334.14142-4-laurent@vivier.eu> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180627232334.14142-1-laurent@vivier.eu> References: <20180627232334.14142-1-laurent@vivier.eu> X-Provags-ID: V03:K1:edM/EcKOOsltjIQ71pp0TVtW+KNC5piPj6TxHqfRNdh5kVRXNPS u6kHm+NTVonne6yAwzWi6yD2+6kidehN2kGXWdQXAFMj05YtaQxR7se+jyXMBmqSV7Ocmje 4NPT7mWaygimHnvghRsE4YhzLIvXaRrbKMbCpDYnKMh3cDkT3JeumG3nnbruH3TLn9mU8J3 5LGGGjaT0XHArMPstnq3Q== X-UI-Out-Filterresults: notjunk:1; V01:K0:h8QL3zWjcog=:uwLtoCACAgPidsJ0wEIfJZ jyl5GJnMqkU33Mq1yzb9LOq91EVFzVJcEPYOeJLPvDbbMROwNGji8PMSxZ+YLYPBHB7iNhow3 k8Z/rGcMRPhFqHfE6vCiplmcunOzp8k64YynWKHrH5Ja29e5jPDYejL+ieyEN5Jd0aJ3PwSYE AQZ7Ez8E9Sr+h5+gn+f31/wQjJDWt9dN9aooAMRcFMmTDZ7GGMqjQrgXBPfh7iuwoPS9fRa8c ehny9iQXwLYjgY4DGZsLpj9rhiToCwaXdzvJONTyZT9Slc8hrSWeLG/YITADyXpuksLZIu9jw 3L+22NSeKI6Fj64NGWM4eTm1dpAmFA2YxNStYXfJcX/Ka29vtv6sA483B4FFT06dw3X80a+yL szB+vRaQDQ62NrZ6LPsLVkM/0D0oboGmgrzPiHZWNkSNhN+J9Qmad10QXgzpltoxDRRjek0fS w23qBhRLg445Ecmu8qW+7z1L34XnLlx5UBsHuSCuHEHQ3NHxU6mTJvZUSv7+zEdr0m9hufiSX MB2dKMB3w4IGVaiv2j6KoOaItKBMJHcSuwpkuwKmRy2wa6nR185BNEj0axXYK1lQR6130WLhV J7vWYpcieKSBbgVsJnFwVOHnm4l1EggZAsM+tQSjvOSl3ztOp7pcWQZeg0emPA4Mk46lYqxid doL9cfc+BIIWMsuXyGNg//vZUP+uclefn8NOJYZ8hzYcmCPXHSbVymcsDJP4Bz9lSllw= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.17.13 Subject: [Qemu-devel] [C v2 03/10] escc: introduce a selector for the register bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , "Dr. David Alan Gilbert" , Fam Zheng , qemu-block@nongnu.org, Jason Wang , Mark Cave-Ayland , Laurent Vivier , Max Reitz , =?utf-8?q?Herv=C3=A9_Poussineau?= , Gerd Hoffmann , Paolo Bonzini , Yongbok Kim , =?utf-8?q?Andreas_F=C3=A4rber?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" On Sparc and PowerMac, the bit 0 of the address selects the register type (control or data) and bit 1 selects the channel (B or A). On m68k Macintosh, the bit 0 selects the channel and bit 1 the register type. This patch introduces a new parameter (bit_swap) to the device interface to indicate bits usage must be swapped between registers and channels. For the moment all the machines use the bit 0, but this change will be needed to emulate Quadra 800. Signed-off-by: Laurent Vivier --- hw/char/escc.c | 30 ++++++++++++++++++++++++------ include/hw/char/escc.h | 1 + 2 files changed, 25 insertions(+), 6 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index 628f5f81f7..cec75b06f9 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -42,14 +42,21 @@ * mouse and keyboard ports don't implement all functions and they are * only asynchronous. There is no DMA. * - * Z85C30 is also used on PowerMacs. There are some small differences - * between Sparc version (sunzilog) and PowerMac (pmac): + * Z85C30 is also used on PowerMacs and m68k Macs. + * + * There are some small differences between Sparc version (sunzilog) + * and PowerMac (pmac): * Offset between control and data registers * There is some kind of lockup bug, but we can ignore it * CTS is inverted * DMA on pmac using DBDMA chip * pmac can do IRDA and faster rates, sunzilog can only do 38400 * pmac baud rate generator clock is 3.6864 MHz, sunzilog 4.9152 MHz + * + * Linux driver for m68k Macs is the same as for PowerMac (pmac_zilog), + * but registers are grouped by type and not by channel: + * channel is selected by bit 0 of the address (instead of bit 1) + * and register is selected by bit 1 of the address (instead of bit 0). */ /* @@ -169,6 +176,16 @@ static void handle_kbd_command(ESCCChannelState *s, int val); static int serial_can_receive(void *opaque); static void serial_receive_byte(ESCCChannelState *s, int ch); +static int reg_shift(ESCCState *s) +{ + return s->bit_swap ? s->it_shift + 1 : s->it_shift; +} + +static int chn_shift(ESCCState *s) +{ + return s->bit_swap ? s->it_shift : s->it_shift + 1; +} + static void clear_queue(void *opaque) { ESCCChannelState *s = opaque; @@ -433,8 +450,8 @@ static void escc_mem_write(void *opaque, hwaddr addr, int newreg, channel; val &= 0xff; - saddr = (addr >> serial->it_shift) & 1; - channel = (addr >> (serial->it_shift + 1)) & 1; + saddr = (addr >> reg_shift(serial)) & 1; + channel = (addr >> chn_shift(serial)) & 1; s = &serial->chn[channel]; switch (saddr) { case SERIAL_CTRL: @@ -537,8 +554,8 @@ static uint64_t escc_mem_read(void *opaque, hwaddr addr, uint32_t ret; int channel; - saddr = (addr >> serial->it_shift) & 1; - channel = (addr >> (serial->it_shift + 1)) & 1; + saddr = (addr >> reg_shift(serial)) & 1; + channel = (addr >> chn_shift(serial)) & 1; s = &serial->chn[channel]; switch (saddr) { case SERIAL_CTRL: @@ -822,6 +839,7 @@ static void escc_realize(DeviceState *dev, Error **errp) static Property escc_properties[] = { DEFINE_PROP_UINT32("frequency", ESCCState, frequency, 0), DEFINE_PROP_UINT32("it_shift", ESCCState, it_shift, 0), + DEFINE_PROP_BOOL("bit_swap", ESCCState, bit_swap, false), DEFINE_PROP_UINT32("disabled", ESCCState, disabled, 0), DEFINE_PROP_UINT32("chnBtype", ESCCState, chn[0].type, 0), DEFINE_PROP_UINT32("chnAtype", ESCCState, chn[1].type, 0), diff --git a/include/hw/char/escc.h b/include/hw/char/escc.h index 42aca83611..8762f61c14 100644 --- a/include/hw/char/escc.h +++ b/include/hw/char/escc.h @@ -50,6 +50,7 @@ typedef struct ESCCState { struct ESCCChannelState chn[2]; uint32_t it_shift; + bool bit_swap; MemoryRegion mmio; uint32_t disabled; uint32_t frequency;