From patchwork Wed Apr 11 18:56:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 897399 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=vivier.eu Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40LvZr3J4sz9s1j for ; Thu, 12 Apr 2018 05:42:43 +1000 (AEST) Received: from localhost ([::1]:50449 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f6Ldg-0003DX-OD for incoming@patchwork.ozlabs.org; Wed, 11 Apr 2018 15:42:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38196) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f6KwD-0006D7-Su for qemu-devel@nongnu.org; Wed, 11 Apr 2018 14:57:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f6Kw8-0007vX-29 for qemu-devel@nongnu.org; Wed, 11 Apr 2018 14:57:45 -0400 Received: from mout.kundenserver.de ([212.227.17.10]:40231) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f6Kw7-0007ue-DL; Wed, 11 Apr 2018 14:57:39 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue105 [212.227.15.183]) with ESMTPSA (Nemesis) id 0LoIBN-1eZj4N2zmL-00gHmj; Wed, 11 Apr 2018 20:57:23 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Wed, 11 Apr 2018 20:56:48 +0200 Message-Id: <20180411185651.21351-17-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180411185651.21351-1-laurent@vivier.eu> References: <20180411185651.21351-1-laurent@vivier.eu> X-Provags-ID: V03:K1:JpyLnEuPI3q6xbPk92FD6zxoaOMElG0wmMiVcmLl4P5HSV0DSb5 8yowvch9tFOOWsTWEVDSKL/PFyI7plm4IsbkDkW9QfYo9ylKvY50ps/9BZQZNaLUVJvpNrL fsozFCrJMIrQWK8NuDG1ZAaLC/+B8MNIqZFc/u+KxrnBfRHPOx2UbHG1RtRYLLZHdrgy2ZV AZ7PcBJ/kuM/tVuQIaRTg== X-UI-Out-Filterresults: notjunk:1; V01:K0:A3KvpyyP9VI=:FlXEimwB+1llyy8mClKx8M 6aw2aB4a4xUH5aE0pkfTe1VIeHQvwNdG861zeQcTOyw9c/MfKK2d/HEdn9VKGKflvYTn1zlar Iap3JQTb/j7lH072KqqTjJYGFabPLYHr7LfoP2DBjU8sXz0ziOGo5V6gKAYwgyiYJtnSR4K01 9wJambrU5oc2GwSolgCM1K1sTRyNIoYs735B+UDS2/36/sbLvcsgoZIHrkbPqXn1bfrusQwNh FXlcLOwAnubQAfBmv+cZxK4BV5pQ+JWZ0gV9/S+h74wVHUhHMpSb6Ai0tOWSgzyWnJXtoEXzz 2NX7sdZ6f9+/LirtTHZLmEKryP3UdIltGgoYtFWEetBh9c+nL06/WcvyYrbCsJVAnr8N9ua7Z pf1vgV+eeFm/G89FxIw8RU2Z1tc8iIZIJ5kAzjiB1BdBGaeWQUWtHqwq0MY51jGclACI3Cqq1 +02MKzuyWjfdN06a+P97QRXfubBPWx61/KEi/INYIqHMIYF4aXJ7E0yx4PhBtFJ5jAqS+7HR4 N1Mm5I0DbBYZAaaateRDwpjI6DzvJ9qGlyBMBhwTM5P0VM2MhJP96Fdi0CxTNLJc8+g0munmc Zhi99T5BE/AlYshoKe3sWE1raUOkkEpi7lbSaAi8quD/yDhNXfA0GdQ7Cs2G+nnVuPdlxGuMW SWzkU0o0/Nz0klHZ0G8oQs4Z4KjRDsrFFNxjVqCQVbwS5CDUo38t6m61GZAg+afzGOAHs7XMw L5zNEliTbjVdUI6I5SXzCocYUZMPRTRHvd+ygw== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.17.10 Subject: [Qemu-devel] [PATCH for 2.13 v2 16/19] linux-user: move tilegx cpu loop to tilegx directory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Cornelia Huck , Riku Voipio , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Laurent Vivier , qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" No code change, only move code from main.c to tilegx/cpu_loop.c. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- linux-user/main.c | 267 ------------------------------------------- linux-user/tilegx/cpu_loop.c | 260 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 260 insertions(+), 267 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index 7f6cfa5548..32922110f1 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -149,262 +149,6 @@ void fork_end(int child) } } -#ifdef TARGET_TILEGX - -static void gen_sigill_reg(CPUTLGState *env) -{ - target_siginfo_t info; - - info.si_signo = TARGET_SIGILL; - info.si_errno = 0; - info.si_code = TARGET_ILL_PRVREG; - info._sifields._sigfault._addr = env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); -} - -static void do_signal(CPUTLGState *env, int signo, int sigcode) -{ - target_siginfo_t info; - - info.si_signo = signo; - info.si_errno = 0; - info._sifields._sigfault._addr = env->pc; - - if (signo == TARGET_SIGSEGV) { - /* The passed in sigcode is a dummy; check for a page mapping - and pass either MAPERR or ACCERR. */ - target_ulong addr = env->excaddr; - info._sifields._sigfault._addr = addr; - if (page_check_range(addr, 1, PAGE_VALID) < 0) { - sigcode = TARGET_SEGV_MAPERR; - } else { - sigcode = TARGET_SEGV_ACCERR; - } - } - info.si_code = sigcode; - - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); -} - -static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr) -{ - env->excaddr = addr; - do_signal(env, TARGET_SIGSEGV, 0); -} - -static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val) -{ - if (unlikely(reg >= TILEGX_R_COUNT)) { - switch (reg) { - case TILEGX_R_SN: - case TILEGX_R_ZERO: - return; - case TILEGX_R_IDN0: - case TILEGX_R_IDN1: - case TILEGX_R_UDN0: - case TILEGX_R_UDN1: - case TILEGX_R_UDN2: - case TILEGX_R_UDN3: - gen_sigill_reg(env); - return; - default: - g_assert_not_reached(); - } - } - env->regs[reg] = val; -} - -/* - * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in - * memory at the address held in the first source register. If the values are - * not equal, then no memory operation is performed. If the values are equal, - * the 8-byte quantity from the second source register is written into memory - * at the address held in the first source register. In either case, the result - * of the instruction is the value read from memory. The compare and write to - * memory are atomic and thus can be used for synchronization purposes. This - * instruction only operates for addresses aligned to a 8-byte boundary. - * Unaligned memory access causes an Unaligned Data Reference interrupt. - * - * Functional Description (64-bit) - * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]); - * rf[Dest] = memVal; - * if (memVal == SPR[CmpValueSPR]) - * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]); - * - * Functional Description (32-bit) - * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA])); - * rf[Dest] = memVal; - * if (memVal == signExtend32 (SPR[CmpValueSPR])) - * memoryWriteWord (rf[SrcA], rf[SrcB]); - * - * - * This function also processes exch and exch4 which need not process SPR. - */ -static void do_exch(CPUTLGState *env, bool quad, bool cmp) -{ - target_ulong addr; - target_long val, sprval; - - start_exclusive(); - - addr = env->atomic_srca; - if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { - goto sigsegv_maperr; - } - - if (cmp) { - if (quad) { - sprval = env->spregs[TILEGX_SPR_CMPEXCH]; - } else { - sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32); - } - } - - if (!cmp || val == sprval) { - target_long valb = env->atomic_srcb; - if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) { - goto sigsegv_maperr; - } - } - - set_regval(env, env->atomic_dstr, val); - end_exclusive(); - return; - - sigsegv_maperr: - end_exclusive(); - gen_sigsegv_maperr(env, addr); -} - -static void do_fetch(CPUTLGState *env, int trapnr, bool quad) -{ - int8_t write = 1; - target_ulong addr; - target_long val, valb; - - start_exclusive(); - - addr = env->atomic_srca; - valb = env->atomic_srcb; - if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { - goto sigsegv_maperr; - } - - switch (trapnr) { - case TILEGX_EXCP_OPCODE_FETCHADD: - case TILEGX_EXCP_OPCODE_FETCHADD4: - valb += val; - break; - case TILEGX_EXCP_OPCODE_FETCHADDGEZ: - valb += val; - if (valb < 0) { - write = 0; - } - break; - case TILEGX_EXCP_OPCODE_FETCHADDGEZ4: - valb += val; - if ((int32_t)valb < 0) { - write = 0; - } - break; - case TILEGX_EXCP_OPCODE_FETCHAND: - case TILEGX_EXCP_OPCODE_FETCHAND4: - valb &= val; - break; - case TILEGX_EXCP_OPCODE_FETCHOR: - case TILEGX_EXCP_OPCODE_FETCHOR4: - valb |= val; - break; - default: - g_assert_not_reached(); - } - - if (write) { - if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) { - goto sigsegv_maperr; - } - } - - set_regval(env, env->atomic_dstr, val); - end_exclusive(); - return; - - sigsegv_maperr: - end_exclusive(); - gen_sigsegv_maperr(env, addr); -} - -void cpu_loop(CPUTLGState *env) -{ - CPUState *cs = CPU(tilegx_env_get_cpu(env)); - int trapnr; - - while (1) { - cpu_exec_start(cs); - trapnr = cpu_exec(cs); - cpu_exec_end(cs); - process_queued_cpu_work(cs); - - switch (trapnr) { - case TILEGX_EXCP_SYSCALL: - { - abi_ulong ret = do_syscall(env, env->regs[TILEGX_R_NR], - env->regs[0], env->regs[1], - env->regs[2], env->regs[3], - env->regs[4], env->regs[5], - env->regs[6], env->regs[7]); - if (ret == -TARGET_ERESTARTSYS) { - env->pc -= 8; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { - env->regs[TILEGX_R_RE] = ret; - env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(ret) ? -ret : 0; - } - break; - } - case TILEGX_EXCP_OPCODE_EXCH: - do_exch(env, true, false); - break; - case TILEGX_EXCP_OPCODE_EXCH4: - do_exch(env, false, false); - break; - case TILEGX_EXCP_OPCODE_CMPEXCH: - do_exch(env, true, true); - break; - case TILEGX_EXCP_OPCODE_CMPEXCH4: - do_exch(env, false, true); - break; - case TILEGX_EXCP_OPCODE_FETCHADD: - case TILEGX_EXCP_OPCODE_FETCHADDGEZ: - case TILEGX_EXCP_OPCODE_FETCHAND: - case TILEGX_EXCP_OPCODE_FETCHOR: - do_fetch(env, trapnr, true); - break; - case TILEGX_EXCP_OPCODE_FETCHADD4: - case TILEGX_EXCP_OPCODE_FETCHADDGEZ4: - case TILEGX_EXCP_OPCODE_FETCHAND4: - case TILEGX_EXCP_OPCODE_FETCHOR4: - do_fetch(env, trapnr, false); - break; - case TILEGX_EXCP_SIGNAL: - do_signal(env, env->signo, env->sigcode); - break; - case TILEGX_EXCP_REG_IDN_ACCESS: - case TILEGX_EXCP_REG_UDN_ACCESS: - gen_sigill_reg(env); - break; - case EXCP_ATOMIC: - cpu_exec_step_atomic(cs); - break; - default: - fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr); - g_assert_not_reached(); - } - process_pending_signals(env); - } -} - -#endif - #ifdef TARGET_RISCV void cpu_loop(CPURISCVState *env) @@ -1583,17 +1327,6 @@ int main(int argc, char **argv, char **envp) env->pc = regs->sepc; env->gpr[xSP] = regs->sp; } -#elif defined(TARGET_TILEGX) - { - int i; - for (i = 0; i < TILEGX_R_COUNT; i++) { - env->regs[i] = regs->regs[i]; - } - for (i = 0; i < TILEGX_SPR_COUNT; i++) { - env->spregs[i] = 0; - } - env->pc = regs->pc; - } #elif defined(TARGET_HPPA) { int i; diff --git a/linux-user/tilegx/cpu_loop.c b/linux-user/tilegx/cpu_loop.c index b7700a5561..4f39eb9ad3 100644 --- a/linux-user/tilegx/cpu_loop.c +++ b/linux-user/tilegx/cpu_loop.c @@ -21,6 +21,266 @@ #include "qemu.h" #include "cpu_loop-common.h" +static void gen_sigill_reg(CPUTLGState *env) +{ + target_siginfo_t info; + + info.si_signo = TARGET_SIGILL; + info.si_errno = 0; + info.si_code = TARGET_ILL_PRVREG; + info._sifields._sigfault._addr = env->pc; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); +} + +static void do_signal(CPUTLGState *env, int signo, int sigcode) +{ + target_siginfo_t info; + + info.si_signo = signo; + info.si_errno = 0; + info._sifields._sigfault._addr = env->pc; + + if (signo == TARGET_SIGSEGV) { + /* The passed in sigcode is a dummy; check for a page mapping + and pass either MAPERR or ACCERR. */ + target_ulong addr = env->excaddr; + info._sifields._sigfault._addr = addr; + if (page_check_range(addr, 1, PAGE_VALID) < 0) { + sigcode = TARGET_SEGV_MAPERR; + } else { + sigcode = TARGET_SEGV_ACCERR; + } + } + info.si_code = sigcode; + + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); +} + +static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr) +{ + env->excaddr = addr; + do_signal(env, TARGET_SIGSEGV, 0); +} + +static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val) +{ + if (unlikely(reg >= TILEGX_R_COUNT)) { + switch (reg) { + case TILEGX_R_SN: + case TILEGX_R_ZERO: + return; + case TILEGX_R_IDN0: + case TILEGX_R_IDN1: + case TILEGX_R_UDN0: + case TILEGX_R_UDN1: + case TILEGX_R_UDN2: + case TILEGX_R_UDN3: + gen_sigill_reg(env); + return; + default: + g_assert_not_reached(); + } + } + env->regs[reg] = val; +} + +/* + * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in + * memory at the address held in the first source register. If the values are + * not equal, then no memory operation is performed. If the values are equal, + * the 8-byte quantity from the second source register is written into memory + * at the address held in the first source register. In either case, the result + * of the instruction is the value read from memory. The compare and write to + * memory are atomic and thus can be used for synchronization purposes. This + * instruction only operates for addresses aligned to a 8-byte boundary. + * Unaligned memory access causes an Unaligned Data Reference interrupt. + * + * Functional Description (64-bit) + * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]); + * rf[Dest] = memVal; + * if (memVal == SPR[CmpValueSPR]) + * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]); + * + * Functional Description (32-bit) + * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA])); + * rf[Dest] = memVal; + * if (memVal == signExtend32 (SPR[CmpValueSPR])) + * memoryWriteWord (rf[SrcA], rf[SrcB]); + * + * + * This function also processes exch and exch4 which need not process SPR. + */ +static void do_exch(CPUTLGState *env, bool quad, bool cmp) +{ + target_ulong addr; + target_long val, sprval; + + start_exclusive(); + + addr = env->atomic_srca; + if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { + goto sigsegv_maperr; + } + + if (cmp) { + if (quad) { + sprval = env->spregs[TILEGX_SPR_CMPEXCH]; + } else { + sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32); + } + } + + if (!cmp || val == sprval) { + target_long valb = env->atomic_srcb; + if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) { + goto sigsegv_maperr; + } + } + + set_regval(env, env->atomic_dstr, val); + end_exclusive(); + return; + + sigsegv_maperr: + end_exclusive(); + gen_sigsegv_maperr(env, addr); +} + +static void do_fetch(CPUTLGState *env, int trapnr, bool quad) +{ + int8_t write = 1; + target_ulong addr; + target_long val, valb; + + start_exclusive(); + + addr = env->atomic_srca; + valb = env->atomic_srcb; + if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { + goto sigsegv_maperr; + } + + switch (trapnr) { + case TILEGX_EXCP_OPCODE_FETCHADD: + case TILEGX_EXCP_OPCODE_FETCHADD4: + valb += val; + break; + case TILEGX_EXCP_OPCODE_FETCHADDGEZ: + valb += val; + if (valb < 0) { + write = 0; + } + break; + case TILEGX_EXCP_OPCODE_FETCHADDGEZ4: + valb += val; + if ((int32_t)valb < 0) { + write = 0; + } + break; + case TILEGX_EXCP_OPCODE_FETCHAND: + case TILEGX_EXCP_OPCODE_FETCHAND4: + valb &= val; + break; + case TILEGX_EXCP_OPCODE_FETCHOR: + case TILEGX_EXCP_OPCODE_FETCHOR4: + valb |= val; + break; + default: + g_assert_not_reached(); + } + + if (write) { + if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) { + goto sigsegv_maperr; + } + } + + set_regval(env, env->atomic_dstr, val); + end_exclusive(); + return; + + sigsegv_maperr: + end_exclusive(); + gen_sigsegv_maperr(env, addr); +} + +void cpu_loop(CPUTLGState *env) +{ + CPUState *cs = CPU(tilegx_env_get_cpu(env)); + int trapnr; + + while (1) { + cpu_exec_start(cs); + trapnr = cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + switch (trapnr) { + case TILEGX_EXCP_SYSCALL: + { + abi_ulong ret = do_syscall(env, env->regs[TILEGX_R_NR], + env->regs[0], env->regs[1], + env->regs[2], env->regs[3], + env->regs[4], env->regs[5], + env->regs[6], env->regs[7]); + if (ret == -TARGET_ERESTARTSYS) { + env->pc -= 8; + } else if (ret != -TARGET_QEMU_ESIGRETURN) { + env->regs[TILEGX_R_RE] = ret; + env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(ret) ? -ret : 0; + } + break; + } + case TILEGX_EXCP_OPCODE_EXCH: + do_exch(env, true, false); + break; + case TILEGX_EXCP_OPCODE_EXCH4: + do_exch(env, false, false); + break; + case TILEGX_EXCP_OPCODE_CMPEXCH: + do_exch(env, true, true); + break; + case TILEGX_EXCP_OPCODE_CMPEXCH4: + do_exch(env, false, true); + break; + case TILEGX_EXCP_OPCODE_FETCHADD: + case TILEGX_EXCP_OPCODE_FETCHADDGEZ: + case TILEGX_EXCP_OPCODE_FETCHAND: + case TILEGX_EXCP_OPCODE_FETCHOR: + do_fetch(env, trapnr, true); + break; + case TILEGX_EXCP_OPCODE_FETCHADD4: + case TILEGX_EXCP_OPCODE_FETCHADDGEZ4: + case TILEGX_EXCP_OPCODE_FETCHAND4: + case TILEGX_EXCP_OPCODE_FETCHOR4: + do_fetch(env, trapnr, false); + break; + case TILEGX_EXCP_SIGNAL: + do_signal(env, env->signo, env->sigcode); + break; + case TILEGX_EXCP_REG_IDN_ACCESS: + case TILEGX_EXCP_REG_UDN_ACCESS: + gen_sigill_reg(env); + break; + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + break; + default: + fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr); + g_assert_not_reached(); + } + process_pending_signals(env); + } +} + void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { + int i; + for (i = 0; i < TILEGX_R_COUNT; i++) { + env->regs[i] = regs->regs[i]; + } + for (i = 0; i < TILEGX_SPR_COUNT; i++) { + env->spregs[i] = 0; + } + env->pc = regs->pc; }