From patchwork Mon Jan 22 17:26:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 864323 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="AvhXhs/T"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zQJRX6srsz9s7s for ; Tue, 23 Jan 2018 04:32:56 +1100 (AEDT) Received: from localhost ([::1]:54942 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edfxm-0002Kx-TP for incoming@patchwork.ozlabs.org; Mon, 22 Jan 2018 12:32:54 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44738) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edfs4-00071R-NQ for qemu-devel@nongnu.org; Mon, 22 Jan 2018 12:27:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1edfs3-0004g2-Vz for qemu-devel@nongnu.org; Mon, 22 Jan 2018 12:27:00 -0500 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:33003) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1edfs3-0004fX-Py for qemu-devel@nongnu.org; Mon, 22 Jan 2018 12:26:59 -0500 Received: by mail-wm0-x242.google.com with SMTP id x4so18473610wmc.0 for ; Mon, 22 Jan 2018 09:26:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fZ5Abu6TieKa9hgICh5l49k34NALWk1BHtQikbbo1TY=; b=AvhXhs/To7LnS5kg+6S80mVSnxF+oxbEE6nrfL+NpSl5+QDGhWqQicq8g9V3qyPur0 24Dtmav4CXebz8pV2MfOYCHbR2VNxPsUkEmosVyybVU4niKbG/I1F8ix2Ax+uH2g3I7t /YJTIJdqk9gmHXO39OVYvC3gCBFOZ3+daCsWQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fZ5Abu6TieKa9hgICh5l49k34NALWk1BHtQikbbo1TY=; b=txg/6EGUiL4cNu98bCmHqFdUcZKzcvsrI1PYp+3xnyt407KBk9TFSwQDTfgk6cjvae us9hElud+CUe4auLSA9yK+7LS3hJo7C6lJcz4a4htrsY6r/ycp1Ps9AFLg2jxpiHXTmi gGUtbjj93bPRhUZP+8WCdu2zPjKtFMEAyUTQKy5/a218mHB93tjRevbreR5Seb7ZTFl/ 3t5btr5kF45ViKNiWbckAQPCbVoCo5DyCUugBO5ERGie1jFTaI+lgve/wLRunqRxnm6n HJP4s9ZKvkYZgx3PDgVBXwcweIbP1xJwUcsEykPEz7NqJHYJLS1sdvjCeg+TY9oqXREO qflw== X-Gm-Message-State: AKwxyteGZIcqOZfxd9IYfuQWlONU5hlBwrUhVc3N21gqWco5/ndP/L/X ubJlUQ8yTzkMPCqtEIl+SEJmnmhvJkg= X-Google-Smtp-Source: AH8x224aL6F0NjVjvcBdWvW38ajgwBdGEfYBJFHrrUtVsjULyyE/mwm7YSFHx82yL53RjvE+XLTMzg== X-Received: by 10.28.15.131 with SMTP id 125mr6134461wmp.24.1516642018523; Mon, 22 Jan 2018 09:26:58 -0800 (PST) Received: from localhost.localdomain ([160.163.176.196]) by smtp.gmail.com with ESMTPSA id f76sm5510900wme.2.2018.01.22.09.26.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 22 Jan 2018 09:26:57 -0800 (PST) From: Ard Biesheuvel To: qemu-devel@nongnu.org Date: Mon, 22 Jan 2018 17:26:43 +0000 Message-Id: <20180122172643.29742-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180122172643.29742-1-ard.biesheuvel@linaro.org> References: <20180122172643.29742-1-ard.biesheuvel@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v5 4/4] target/arm: enable user-mode SHA-3, SM3 and SHA-512 instruction support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Ard Biesheuvel Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add support for the new ARMv8.2 SHA-3, SM3 and SHA-512 instructions to AArch64 user mode emulation. Reviewed-by: Peter Maydell Signed-off-by: Ard Biesheuvel --- linux-user/elfload.c | 18 ++++++++++++++++++ target/arm/cpu64.c | 3 +++ 2 files changed, 21 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 20f3d8c2c373..5d5aa26d2710 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -512,6 +512,21 @@ enum { ARM_HWCAP_A64_SHA1 = 1 << 5, ARM_HWCAP_A64_SHA2 = 1 << 6, ARM_HWCAP_A64_CRC32 = 1 << 7, + ARM_HWCAP_A64_ATOMICS = 1 << 8, + ARM_HWCAP_A64_FPHP = 1 << 9, + ARM_HWCAP_A64_ASIMDHP = 1 << 10, + ARM_HWCAP_A64_CPUID = 1 << 11, + ARM_HWCAP_A64_ASIMDRDM = 1 << 12, + ARM_HWCAP_A64_JSCVT = 1 << 13, + ARM_HWCAP_A64_FCMA = 1 << 14, + ARM_HWCAP_A64_LRCPC = 1 << 15, + ARM_HWCAP_A64_DCPOP = 1 << 16, + ARM_HWCAP_A64_SHA3 = 1 << 17, + ARM_HWCAP_A64_SM3 = 1 << 18, + ARM_HWCAP_A64_SM4 = 1 << 19, + ARM_HWCAP_A64_ASIMDDP = 1 << 20, + ARM_HWCAP_A64_SHA512 = 1 << 21, + ARM_HWCAP_A64_SVE = 1 << 22, }; #define ELF_HWCAP get_elf_hwcap() @@ -532,6 +547,9 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP_A64_SHA1); GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP_A64_SHA2); GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32); + GET_FEATURE(ARM_FEATURE_V8_SHA3, ARM_HWCAP_A64_SHA3); + GET_FEATURE(ARM_FEATURE_V8_SM3, ARM_HWCAP_A64_SM3); + GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512); #undef GET_FEATURE return hwcaps; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 670c07ab6ed4..56d50ba57194 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -224,6 +224,9 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_AES); set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); + set_feature(&cpu->env, ARM_FEATURE_V8_SM3); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */