From patchwork Thu May 25 21:04:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 767135 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wYhp13GL6z9s8N for ; Fri, 26 May 2017 07:13:45 +1000 (AEST) Received: from localhost ([::1]:33720 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dE04k-00065G-Ux for incoming@patchwork.ozlabs.org; Thu, 25 May 2017 17:13:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55200) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dDzwb-0005dl-Vb for qemu-devel@nongnu.org; Thu, 25 May 2017 17:05:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dDzwZ-0001LF-UX for qemu-devel@nongnu.org; Thu, 25 May 2017 17:05:17 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:37408) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dDzwZ-0001Jv-NE for qemu-devel@nongnu.org; Thu, 25 May 2017 17:05:15 -0400 Received: from [2001:bc8:30d7:121:cc44:2c6c:4d9c:42c0] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1dDzwX-0008RF-Rr; Thu, 25 May 2017 23:05:13 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1dDzwW-0001K0-A4; Thu, 25 May 2017 23:05:12 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Thu, 25 May 2017 23:04:55 +0200 Message-Id: <20170525210508.4910-14-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170525210508.4910-1-aurelien@aurel32.net> References: <20170525210508.4910-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PATCH 13/26] target/s390x: improve 24-bit and 31-bit addresses write X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexander Graf , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Aurelien Jarno Reviewed-by: Richard Henderson --- target/s390x/mem_helper.c | 37 ++++++++++++++++++++++++++++++------- 1 file changed, 30 insertions(+), 7 deletions(-) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 2b0cde13b4..bbb3eceb71 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -398,6 +398,29 @@ static inline uint64_t get_address(CPUS390XState *env, int reg) return wrap_address(env, env->regs[reg]); } +static inline void set_address(CPUS390XState *env, int reg, uint64_t address) +{ + if (env->psw.mask & PSW_MASK_64) { + /* 64-Bit mode */ + env->regs[reg] = address; + } else { + if (!(env->psw.mask & PSW_MASK_32)) { + /* 24-Bit mode. According to the PoO it is implementation + dependent if bits 32-39 remain unchanged or are set to + zeros. Choose the former so that the function can also be + used for TRT. */ + env->regs[reg] = deposit64(env->regs[reg], 0, 24, address); + } else { + /* 31-Bit mode. According to the PoO it is implementation + dependent if bit 32 remains unchanged or is set to zero. + Choose the latter so that the function can also be used for + TRT. */ + address &= 0x7fffffff; + env->regs[reg] = deposit64(env->regs[reg], 0, 32, address); + } + } +} + /* search string (c is byte to search, r2 is string, r1 end of string) */ uint64_t HELPER(srst)(CPUS390XState *env, uint64_t r0, uint64_t end, uint64_t str) @@ -609,8 +632,8 @@ uint32_t HELPER(mvcl)(CPUS390XState *env, uint32_t r1, uint32_t r2) env->regs[r1 + 1] = destlen; /* can't use srclen here, we trunc'ed it */ env->regs[r2 + 1] -= src - env->regs[r2]; - env->regs[r1] = dest; - env->regs[r2] = src; + set_address(env, r1, dest); + set_address(env, r2, src); return cc; } @@ -658,8 +681,8 @@ uint32_t HELPER(mvcle)(CPUS390XState *env, uint32_t r1, uint64_t a2, /* can't use srclen here, we trunc'ed it */ /* FIXME: 31-bit mode! */ env->regs[r3 + 1] -= src - env->regs[r3]; - env->regs[r1] = dest; - env->regs[r3] = src; + set_address(env, r1, dest); + set_address(env, r3, src); return cc; } @@ -696,8 +719,8 @@ uint32_t HELPER(clcle)(CPUS390XState *env, uint32_t r1, uint64_t a2, env->regs[r1 + 1] = destlen; /* can't use srclen here, we trunc'ed it */ env->regs[r3 + 1] -= src - env->regs[r3]; - env->regs[r1] = dest; - env->regs[r3] = src; + set_address(env, r1, dest); + set_address(env, r3, src); return cc; } @@ -901,7 +924,7 @@ static uint32_t do_helper_trt(CPUS390XState *env, uint32_t len, uint64_t array, uint8_t sbyte = cpu_ldub_data_ra(env, trans + byte, ra); if (sbyte != 0) { - env->regs[1] = array + i; + set_address(env, 1, array + i); env->regs[2] = deposit64(env->regs[2], 0, 8, sbyte); return (i == len) ? 2 : 1; }