From patchwork Tue May 16 23:01:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 763222 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wSCf26wssz9s2Q for ; Wed, 17 May 2017 09:02:50 +1000 (AEST) Received: from localhost ([::1]:44492 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dAlUN-00080Q-65 for incoming@patchwork.ozlabs.org; Tue, 16 May 2017 19:02:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50512) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dAlTn-0007y4-PI for qemu-devel@nongnu.org; Tue, 16 May 2017 19:02:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dAlTm-0002dT-Tx for qemu-devel@nongnu.org; Tue, 16 May 2017 19:02:11 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:45178) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dAlTm-0002d1-OD for qemu-devel@nongnu.org; Tue, 16 May 2017 19:02:10 -0400 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1dAlTk-00021N-HF; Wed, 17 May 2017 01:02:08 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1dAlTj-00022S-Qg; Wed, 17 May 2017 01:02:07 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Wed, 17 May 2017 01:01:59 +0200 Message-Id: <20170516230159.4195-5-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170516230159.4195-1-aurelien@aurel32.net> References: <20170516230159.4195-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PATCH 4/4] target/mips: optimize WSBH, DSBH and DSHD X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yongbok Kim , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Use the same mask to avoid having to load two different constants, as suggested by Richard Henderson. Signed-off-by: Aurelien Jarno Reviewed-by: Richard Henderson --- target/mips/translate.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 3022f349cb..c71eed498c 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4572,12 +4572,14 @@ static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd) case OPC_WSBH: { TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_const_tl(0x00FF00FF); tcg_gen_shri_tl(t1, t0, 8); - tcg_gen_andi_tl(t1, t1, 0x00FF00FF); + tcg_gen_and_tl(t1, t1, t2); + tcg_gen_and_tl(t0, t0, t2); tcg_gen_shli_tl(t0, t0, 8); - tcg_gen_andi_tl(t0, t0, ~0x00FF00FF); tcg_gen_or_tl(t0, t0, t1); + tcg_temp_free(t2); tcg_temp_free(t1); tcg_gen_ext32s_tl(cpu_gpr[rd], t0); } @@ -4592,27 +4594,31 @@ static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd) case OPC_DSBH: { TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_const_tl(0x00FF00FF00FF00FFULL); tcg_gen_shri_tl(t1, t0, 8); - tcg_gen_andi_tl(t1, t1, 0x00FF00FF00FF00FFULL); + tcg_gen_and_tl(t1, t1, t2); + tcg_gen_and_tl(t0, t0, t2); tcg_gen_shli_tl(t0, t0, 8); - tcg_gen_andi_tl(t0, t0, ~0x00FF00FF00FF00FFULL); tcg_gen_or_tl(cpu_gpr[rd], t0, t1); + tcg_temp_free(t2); tcg_temp_free(t1); } break; case OPC_DSHD: { TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_const_tl(0x0000FFFF0000FFFFULL); tcg_gen_shri_tl(t1, t0, 16); - tcg_gen_andi_tl(t1, t1, 0x0000FFFF0000FFFFULL); + tcg_gen_and_tl(t1, t1, t2); + tcg_gen_and_tl(t0, t0, t2); tcg_gen_shli_tl(t0, t0, 16); - tcg_gen_andi_tl(t0, t0, ~0x0000FFFF0000FFFFULL); tcg_gen_or_tl(t0, t0, t1); tcg_gen_shri_tl(t1, t0, 32); tcg_gen_shli_tl(t0, t0, 32); tcg_gen_or_tl(cpu_gpr[rd], t0, t1); + tcg_temp_free(t2); tcg_temp_free(t1); } break;