From patchwork Tue May 16 23:01:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 763224 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wSChY2Ghtz9s2Q for ; Wed, 17 May 2017 09:05:01 +1000 (AEST) Received: from localhost ([::1]:44499 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dAlWU-00018r-Pb for incoming@patchwork.ozlabs.org; Tue, 16 May 2017 19:04:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50520) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dAlTo-0007yI-05 for qemu-devel@nongnu.org; Tue, 16 May 2017 19:02:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dAlTn-0002dt-8y for qemu-devel@nongnu.org; Tue, 16 May 2017 19:02:12 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:45192) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dAlTn-0002dB-3I; Tue, 16 May 2017 19:02:11 -0400 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1dAlTk-00021K-90; Wed, 17 May 2017 01:02:08 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1dAlTj-000223-Gf; Wed, 17 May 2017 01:02:07 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Wed, 17 May 2017 01:01:56 +0200 Message-Id: <20170516230159.4195-2-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170516230159.4195-1-aurelien@aurel32.net> References: <20170516230159.4195-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PATCH 1/4] target/arm: optimize aarch32 rev16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "open list:ARM" , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Use the same mask to avoid having to load two different constants, as suggested by Richard Henderson. Signed-off-by: Aurelien Jarno Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/translate.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 0b5a0bca06..5becb2bb89 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -339,11 +339,13 @@ static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) static void gen_rev16(TCGv_i32 var) { TCGv_i32 tmp = tcg_temp_new_i32(); + TCGv_i32 mask = tcg_const_i32(0x00ff00ff); tcg_gen_shri_i32(tmp, var, 8); - tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff); + tcg_gen_and_i32(tmp, tmp, mask); + tcg_gen_and_i32(var, var, mask); tcg_gen_shli_i32(var, var, 8); - tcg_gen_andi_i32(var, var, 0xff00ff00); tcg_gen_or_i32(var, var, tmp); + tcg_temp_free_i32(mask); tcg_temp_free_i32(tmp); }