From patchwork Tue May 9 08:27:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 759966 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wMXZr0KT2z9s3T for ; Tue, 9 May 2017 18:28:52 +1000 (AEST) Received: from localhost ([::1]:35746 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d80Vl-0002jp-EB for incoming@patchwork.ozlabs.org; Tue, 09 May 2017 04:28:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49324) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d80V7-0002hc-Lc for qemu-devel@nongnu.org; Tue, 09 May 2017 04:28:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d80V6-00005v-R9 for qemu-devel@nongnu.org; Tue, 09 May 2017 04:28:09 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:35422) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d80V6-00005a-KW for qemu-devel@nongnu.org; Tue, 09 May 2017 04:28:08 -0400 Received: from ohm.aurel32.net ([2001:bc8:30d7:111::1000]) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1d80V5-0003hd-1u; Tue, 09 May 2017 10:28:07 +0200 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.89) (envelope-from ) id 1d80V4-0002oU-Kh; Tue, 09 May 2017 10:28:06 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Tue, 9 May 2017 10:27:58 +0200 Message-Id: <20170509082800.10756-2-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170509082800.10756-1-aurelien@aurel32.net> References: <20170509082800.10756-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PATCH 1/3] target/s390x: mask the SIGP order_code using SIGP_ORDER_MASK X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Cornelia Huck , Christian Borntraeger , Alexander Graf , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" For that move the definition from kvm.c to cpu.h Signed-off-by: Aurelien Jarno Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson Reviewed-by: Cornelia Huck Reviewed-by: Philippe Mathieu-Daudé --- target/s390x/cpu.h | 3 +++ target/s390x/kvm.c | 2 -- target/s390x/misc_helper.c | 3 +-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index df823280a5..2471db920d 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -1081,6 +1081,9 @@ struct sysib_322 { #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2 +/* SIGP order code mask corresponding to bit positions 56-63 */ +#define SIGP_ORDER_MASK 0x000000ff + void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr); int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc, target_ulong *raddr, int *flags, bool exc); diff --git a/target/s390x/kvm.c b/target/s390x/kvm.c index 1a249d8359..fb105429be 100644 --- a/target/s390x/kvm.c +++ b/target/s390x/kvm.c @@ -1764,8 +1764,6 @@ static int sigp_set_architecture(S390CPU *cpu, uint32_t param, return SIGP_CC_ORDER_CODE_ACCEPTED; } -#define SIGP_ORDER_MASK 0x000000ff - static int handle_sigp(S390CPU *cpu, struct kvm_run *run, uint8_t ipa1) { CPUS390XState *env = &cpu->env; diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c index 53cb3b8ac6..395f38dea5 100644 --- a/target/s390x/misc_helper.c +++ b/target/s390x/misc_helper.c @@ -521,8 +521,7 @@ uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1, qemu_mutex_lock_iothread(); - /* sigp contains the order code in bit positions 56-63, mask it here. */ - switch (order_code & 0xff) { + switch (order_code & SIGP_ORDER_MASK) { case SIGP_SET_ARCH: cc = SIGP_CC_ORDER_CODE_ACCEPTED; /* switch arch */