From patchwork Tue Oct 11 18:40:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christopher Covington X-Patchwork-Id: 680859 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3stm7c2yZNz9s3T for ; Wed, 12 Oct 2016 05:42:20 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=codeaurora.org header.i=@codeaurora.org header.b=PkOJ+C5s4YAvSvXN/xQosxuOXw2aDrParRxsI5MElbgpKNTlDeyD4yRM4SOtMccp2iOgcyWFGycwAzTz2aoaVUkr8u7BCbfPU4r647YU/1Zq3k6dBrE8lA2tivB5SGwfyHIoI7jSwB/0+/BSonD4O8rsBXClNSBm+s0OoA7/EPM=; dkim=fail reason="signature verification failed" (1024-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b=PkOJ+C5s4YAvSvXN/xQosxuOXw2aDrParRxsI5MElbgpKNTlDeyD4yRM4SOtMccp2iOgcyWFGycwAzTz2aoaVUkr8u7BCbfPU4r647YU/1Zq3k6dBrE8lA2tivB5SGwfyHIoI7jSwB/0+/BSonD4O8rsBXClNSBm+s0OoA7/EPM=; dkim-atps=neutral Received: from localhost ([::1]:57414 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bu20F-0008NI-N3 for incoming@patchwork.ozlabs.org; Tue, 11 Oct 2016 14:42:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53380) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bu1z4-0007ZS-90 for qemu-devel@nongnu.org; Tue, 11 Oct 2016 14:41:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bu1z0-0003R7-8N for qemu-devel@nongnu.org; Tue, 11 Oct 2016 14:41:02 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:56510) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bu1yz-0003Qq-Sb for qemu-devel@nongnu.org; Tue, 11 Oct 2016 14:40:58 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 9430D61768; Tue, 11 Oct 2016 18:40:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1476211256; bh=tkhpoll7GPhPnwFrWXdGWzIxq29hvs7VuoHhfllPrnE=; h=From:To:Cc:Subject:Date:From; b=PkOJ+C5s4YAvSvXN/xQosxuOXw2aDrParRxsI5MElbgpKNTlDeyD4yRM4SOtMccp2 iOgcyWFGycwAzTz2aoaVUkr8u7BCbfPU4r647YU/1Zq3k6dBrE8lA2tivB5SGwfyHI oI7jSwB/0+/BSonD4O8rsBXClNSBm+s0OoA7/EPM= Received: from rtp-lab-has1.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: cov@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 9420A61707; Tue, 11 Oct 2016 18:40:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1476211256; bh=tkhpoll7GPhPnwFrWXdGWzIxq29hvs7VuoHhfllPrnE=; h=From:To:Cc:Subject:Date:From; b=PkOJ+C5s4YAvSvXN/xQosxuOXw2aDrParRxsI5MElbgpKNTlDeyD4yRM4SOtMccp2 iOgcyWFGycwAzTz2aoaVUkr8u7BCbfPU4r647YU/1Zq3k6dBrE8lA2tivB5SGwfyHI oI7jSwB/0+/BSonD4O8rsBXClNSBm+s0OoA7/EPM= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 9420A61707 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=cov@codeaurora.org From: Christopher Covington To: Andrew Jones , qemu-devel@nongnu.org Date: Tue, 11 Oct 2016 14:40:42 -0400 Message-Id: <20161011184044.28373-1-cov@codeaurora.org> X-Mailer: git-send-email 2.9.3 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [kvm-unit-tests PATCHv6 1/3] arm: Add PMU test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Wei Huang , Christopher Covington Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Beginning with a simple sanity check of the control register, add a unit test for the ARM Performance Monitors Unit (PMU). As of October 2016, whether KVM mode has a PMU at all is a tricky question of which QEMU / mach-virt version is used. So only enable the TCG mode tests for now. Signed-off-by: Christopher Covington Reviewed-by: Andrew Jones --- arm/Makefile.common | 3 +- arm/pmu.c | 82 +++++++++++++++++++++++++++++++++++++++++++++++++++++ arm/unittests.cfg | 14 +++++++++ 3 files changed, 98 insertions(+), 1 deletion(-) create mode 100644 arm/pmu.c diff --git a/arm/Makefile.common b/arm/Makefile.common index ccb554d..f98f422 100644 --- a/arm/Makefile.common +++ b/arm/Makefile.common @@ -11,7 +11,8 @@ endif tests-common = \ $(TEST_DIR)/selftest.flat \ - $(TEST_DIR)/spinlock-test.flat + $(TEST_DIR)/spinlock-test.flat \ + $(TEST_DIR)/pmu.flat all: test_cases diff --git a/arm/pmu.c b/arm/pmu.c new file mode 100644 index 0000000..42d0ee1 --- /dev/null +++ b/arm/pmu.c @@ -0,0 +1,82 @@ +/* + * Test the ARM Performance Monitors Unit (PMU). + * + * Copyright 2015 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License version 2.1 and + * only version 2.1 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License + * for more details. + */ +#include "libcflat.h" + +#if defined(__arm__) +static inline uint32_t get_pmcr(void) +{ + uint32_t ret; + + asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (ret)); + return ret; +} +#elif defined(__aarch64__) +static inline uint32_t get_pmcr(void) +{ + uint32_t ret; + + asm volatile("mrs %0, pmcr_el0" : "=r" (ret)); + return ret; +} +#endif + +struct pmu_data { + union { + uint32_t pmcr_el0; + struct { + uint32_t enable:1; + uint32_t event_counter_reset:1; + uint32_t cycle_counter_reset:1; + uint32_t cycle_counter_clock_divider:1; + uint32_t event_counter_export:1; + uint32_t cycle_counter_disable_when_prohibited:1; + uint32_t cycle_counter_long:1; + uint32_t reserved:4; + uint32_t counters:5; + uint32_t identification_code:8; + uint32_t implementer:8; + }; + }; +}; + +/* + * As a simple sanity check on the PMCR_EL0, ensure the implementer field isn't + * null. Also print out a couple other interesting fields for diagnostic + * purposes. For example, as of fall 2015, QEMU TCG mode doesn't implement + * event counters and therefore reports zero event counters, but hopefully + * support for at least the instructions event will be added in the future and + * the reported number of event counters will become nonzero. + */ +static bool check_pmcr(void) +{ + struct pmu_data pmu; + + pmu.pmcr_el0 = get_pmcr(); + + printf("PMU implementer: %c\n", pmu.implementer); + printf("Identification code: 0x%x\n", pmu.identification_code); + printf("Event counters: %d\n", pmu.counters); + + return pmu.implementer != 0; +} + +int main(void) +{ + report_prefix_push("pmu"); + + report("Control register", check_pmcr()); + + return report_summary(); +} diff --git a/arm/unittests.cfg b/arm/unittests.cfg index ffd12e5..edaed4a 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -51,3 +51,17 @@ file = selftest.flat smp = $MAX_SMP extra_params = -append 'smp' groups = selftest + +# Test PMU support with -icount IPC=1 +[pmu-icount-1] +file = pmu.flat +extra_params = -icount 0 -append '1' +groups = pmu +accel = tcg + +# Test PMU support with -icount IPC=256 +[pmu-icount-256] +file = pmu.flat +extra_params = -icount 8 -append '256' +groups = pmu +accel = tcg