From patchwork Thu Sep 8 14:51:53 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Burton X-Patchwork-Id: 667766 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3sVTxd5R7Zz9s2Q for ; Fri, 9 Sep 2016 04:53:25 +1000 (AEST) Received: from localhost ([::1]:50738 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bi4Rt-00077F-E0 for incoming@patchwork.ozlabs.org; Thu, 08 Sep 2016 14:53:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36343) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bi0hb-0000bT-7p for qemu-devel@nongnu.org; Thu, 08 Sep 2016 10:53:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bi0hX-0000dk-Hj for qemu-devel@nongnu.org; Thu, 08 Sep 2016 10:53:18 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:32487) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bi0hX-0000dc-9O for qemu-devel@nongnu.org; Thu, 08 Sep 2016 10:53:15 -0400 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Forcepoint Email with ESMTPS id E622D9D7A3FC1; Thu, 8 Sep 2016 15:52:59 +0100 (IST) Received: from localhost (10.100.200.230) by HHMAIL01.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0; Thu, 8 Sep 2016 15:53:03 +0100 From: Paul Burton To: , Aurelien Jarno , Leon Alrae Date: Thu, 8 Sep 2016 15:51:53 +0100 Message-ID: <20160908145158.30720-4-paul.burton@imgtec.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20160908145158.30720-1-paul.burton@imgtec.com> References: <20160908145158.30720-1-paul.burton@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.200.230] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PATCH v2 3/8] hw/mips_gic: Update pin state on mask changes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Burton Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" If the GIC interrupt mask is changed by a write to the smask (set mask) or rmask (reset mask) registers, we need to re-evaluate the state of the pins/IRQs fed to the CPU. Without doing so we risk leaving a pin high despite the interrupt that led to that state being masked, or losing interrupts if an already pending interrupt is unmasked. Signed-off-by: Paul Burton Reviewed-by: Leon Alrae --- hw/intc/mips_gic.c | 56 ++++++++++++++++++++++++++++++------------------------ 1 file changed, 31 insertions(+), 25 deletions(-) diff --git a/hw/intc/mips_gic.c b/hw/intc/mips_gic.c index 6e25773..15e6e40 100644 --- a/hw/intc/mips_gic.c +++ b/hw/intc/mips_gic.c @@ -20,31 +20,29 @@ #include "kvm_mips.h" #include "hw/intc/mips_gic.h" -static void mips_gic_set_vp_irq(MIPSGICState *gic, int vp, int pin, int level) +static void mips_gic_set_vp_irq(MIPSGICState *gic, int vp, int pin) { - int ored_level = level; + int ored_level = 0; int i; /* ORing pending registers sharing same pin */ - if (!ored_level) { - for (i = 0; i < gic->num_irq; i++) { - if ((gic->irq_state[i].map_pin & GIC_MAP_MSK) == pin && - gic->irq_state[i].map_vp == vp && - gic->irq_state[i].enabled) { - ored_level |= gic->irq_state[i].pending; - } - if (ored_level) { - /* no need to iterate all interrupts */ - break; - } + for (i = 0; i < gic->num_irq; i++) { + if ((gic->irq_state[i].map_pin & GIC_MAP_MSK) == pin && + gic->irq_state[i].map_vp == vp && + gic->irq_state[i].enabled) { + ored_level |= gic->irq_state[i].pending; } - if (((gic->vps[vp].compare_map & GIC_MAP_MSK) == pin) && - (gic->vps[vp].mask & GIC_VP_MASK_CMP_MSK)) { - /* ORing with local pending register (count/compare) */ - ored_level |= (gic->vps[vp].pend & GIC_VP_MASK_CMP_MSK) >> - GIC_VP_MASK_CMP_SHF; + if (ored_level) { + /* no need to iterate all interrupts */ + break; } } + if (((gic->vps[vp].compare_map & GIC_MAP_MSK) == pin) && + (gic->vps[vp].mask & GIC_VP_MASK_CMP_MSK)) { + /* ORing with local pending register (count/compare) */ + ored_level |= (gic->vps[vp].pend & GIC_VP_MASK_CMP_MSK) >> + GIC_VP_MASK_CMP_SHF; + } if (kvm_enabled()) { kvm_mips_set_ipi_interrupt(mips_env_get_cpu(gic->vps[vp].env), pin + GIC_CPU_PIN_OFFSET, @@ -55,21 +53,27 @@ static void mips_gic_set_vp_irq(MIPSGICState *gic, int vp, int pin, int level) } } -static void gic_set_irq(void *opaque, int n_IRQ, int level) +static void gic_update_pin_for_irq(MIPSGICState *gic, int n_IRQ) { - MIPSGICState *gic = (MIPSGICState *) opaque; int vp = gic->irq_state[n_IRQ].map_vp; int pin = gic->irq_state[n_IRQ].map_pin & GIC_MAP_MSK; + if (vp < 0 || vp >= gic->num_vps) { + return; + } + mips_gic_set_vp_irq(gic, vp, pin); +} + +static void gic_set_irq(void *opaque, int n_IRQ, int level) +{ + MIPSGICState *gic = (MIPSGICState *) opaque; + gic->irq_state[n_IRQ].pending = (uint8_t) level; if (!gic->irq_state[n_IRQ].enabled) { /* GIC interrupt source disabled */ return; } - if (vp < 0 || vp >= gic->num_vps) { - return; - } - mips_gic_set_vp_irq(gic, vp, pin, level); + gic_update_pin_for_irq(gic, n_IRQ); } #define OFFSET_CHECK(c) \ @@ -209,7 +213,7 @@ static void gic_timer_store_vp_compare(MIPSGICState *gic, uint32_t vp_index, gic->vps[vp_index].pend &= ~(1 << GIC_LOCAL_INT_COMPARE); if (gic->vps[vp_index].compare_map & GIC_MAP_TO_PIN_MSK) { uint32_t pin = (gic->vps[vp_index].compare_map & GIC_MAP_MSK); - mips_gic_set_vp_irq(gic, vp_index, pin, 0); + mips_gic_set_vp_irq(gic, vp_index, pin); } mips_gictimer_store_vp_compare(gic->gic_timer, vp_index, compare); } @@ -286,6 +290,7 @@ static void gic_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) OFFSET_CHECK((base + size * 8) <= gic->num_irq); for (i = 0; i < size * 8; i++) { gic->irq_state[base + i].enabled &= !((data >> i) & 1); + gic_update_pin_for_irq(gic, base + i); } break; case GIC_SH_WEDGE_OFS: @@ -305,6 +310,7 @@ static void gic_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) OFFSET_CHECK((base + size * 8) <= gic->num_irq); for (i = 0; i < size * 8; i++) { gic->irq_state[base + i].enabled |= (data >> i) & 1; + gic_update_pin_for_irq(gic, base + i); } break; case GIC_SH_MAP0_PIN_OFS ... GIC_SH_MAP255_PIN_OFS: