From patchwork Tue Apr 28 17:52:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Williamson X-Patchwork-Id: 465724 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8869014012C for ; Wed, 29 Apr 2015 03:53:09 +1000 (AEST) Received: from localhost ([::1]:35284 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yn9gx-0001Y9-Rw for incoming@patchwork.ozlabs.org; Tue, 28 Apr 2015 13:53:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39197) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yn9gU-0000o3-BT for qemu-devel@nongnu.org; Tue, 28 Apr 2015 13:52:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yn9gT-0005uJ-Bu for qemu-devel@nongnu.org; Tue, 28 Apr 2015 13:52:38 -0400 Received: from mx1.redhat.com ([209.132.183.28]:51631) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yn9gT-0005u5-18 for qemu-devel@nongnu.org; Tue, 28 Apr 2015 13:52:37 -0400 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id t3SHqa4Q010605 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Tue, 28 Apr 2015 13:52:36 -0400 Received: from gimli.home (ovpn-113-195.phx2.redhat.com [10.3.113.195]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id t3SHqZck006548; Tue, 28 Apr 2015 13:52:36 -0400 From: Alex Williamson To: qemu-devel@nongnu.org Date: Tue, 28 Apr 2015 11:52:35 -0600 Message-ID: <20150428175235.22974.29960.stgit@gimli.home> In-Reply-To: <20150428175126.22974.5772.stgit@gimli.home> References: <20150428175126.22974.5772.stgit@gimli.home> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 1/3] vfio-pci: Further fix BAR size overflow X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In an analysis by Laszlo, the resulting type of our calculation for the end of the MSI-X table, and thus the start of memory after the table, is uint32_t. We're therefore not correctly preventing the corner case overflow that we intended to fix here where a BAR >=4G could place the MSI-X table to end exactly at the 4G boundary. The MSI-X table offset is defined by the hardware spec to 32bits, so we simply use a cast rather than changing data structure types. This scenario is purely theoretically, typically the MSI-X table is located at the front of the BAR. Reported-by: Laszlo Ersek Reviewed-by: Laszlo Ersek Signed-off-by: Alex Williamson --- hw/vfio/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index cd15b20..495f5fd 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -2400,7 +2400,7 @@ static void vfio_map_bar(VFIOPCIDevice *vdev, int nr) if (vdev->msix && vdev->msix->table_bar == nr) { uint64_t start; - start = HOST_PAGE_ALIGN(vdev->msix->table_offset + + start = HOST_PAGE_ALIGN((uint64_t)vdev->msix->table_offset + (vdev->msix->entries * PCI_MSIX_ENTRY_SIZE)); size = start < bar->region.size ? bar->region.size - start : 0;