From patchwork Wed Aug 13 19:09:41 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Williamson X-Patchwork-Id: 379730 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C9A121400B2 for ; Thu, 14 Aug 2014 05:13:30 +1000 (EST) Received: from localhost ([::1]:49741 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XHdzE-0000uc-Tu for incoming@patchwork.ozlabs.org; Wed, 13 Aug 2014 15:13:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56204) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XHdvj-0003YT-8d for qemu-devel@nongnu.org; Wed, 13 Aug 2014 15:09:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XHdvc-0005Q4-NK for qemu-devel@nongnu.org; Wed, 13 Aug 2014 15:09:51 -0400 Received: from mx1.redhat.com ([209.132.183.28]:63092) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XHdvc-0005PZ-GA; Wed, 13 Aug 2014 15:09:44 -0400 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id s7DJ9gCH023096 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 13 Aug 2014 15:09:43 -0400 Received: from gimli.home (ovpn-113-173.phx2.redhat.com [10.3.113.173]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id s7DJ9fvW018271; Wed, 13 Aug 2014 15:09:42 -0400 From: Alex Williamson To: qemu-devel@nongnu.org, kvm@vger.kernel.org Date: Wed, 13 Aug 2014 13:09:41 -0600 Message-ID: <20140813190916.12400.59842.stgit@gimli.home> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.68 on 10.5.11.27 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: Alex Williamson , lersek@redhat.com, qemu-stable@nongnu.org Subject: [Qemu-devel] [PATCH] x86: Reset MTRR on vCPU reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The SDM specifies (June 2014 Vol3 11.11.5): On a hardware reset, the P6 and more recent processors clear the valid flags in variable-range MTRRs and clear the E flag in the IA32_MTRR_DEF_TYPE MSR to disable all MTRRs. All other bits in the MTRRs are undefined. We currently do none of that, so whatever MTRR settings you had prior to reset is what you have after reset. Usually this doesn't matter because KVM often ignores the guest mappings and uses write-back anyway. However, if you have an assigned device and an IOMMU that allows NoSnoop for that device, KVM defers to the guest memory mappings which are now stale after reset. The result is that OVMF rebooting on such a configuration takes a full minute to LZMA decompress the EFI volume, a process that is nearly instant on the initial boot. Add support for reseting the SDM defined bits on vCPU reset. Also, by my count we're already in danger of overflowing the entries array that we pass to KVM, so I've topped it up for a bit of headroom. Signed-off-by: Alex Williamson Cc: qemu-stable@nongnu.org --- target-i386/cpu.c | 6 ++++++ target-i386/cpu.h | 4 ++++ target-i386/kvm.c | 14 +++++++++++++- 3 files changed, 23 insertions(+), 1 deletion(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 6d008ab..b5ae654 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2588,6 +2588,12 @@ static void x86_cpu_reset(CPUState *s) env->xcr0 = 1; + /* MTRR init - Clear global enable bit and valid bit in each variable reg */ + env->mtrr_deftype &= ~MSR_MTRRdefType_Enable; + for (i = 0; i < MSR_MTRRcap_VCNT; i++) { + env->mtrr_var[i].mask &= ~MSR_MTRRphysMask_Valid; + } + #if !defined(CONFIG_USER_ONLY) /* We hard-wire the BSP to the first CPU. */ if (s->cpu_index == 0) { diff --git a/target-i386/cpu.h b/target-i386/cpu.h index e634d83..139890f 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -337,6 +337,8 @@ #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) +#define MSR_MTRRphysMask_Valid (1 << 11) + #define MSR_MTRRfix64K_00000 0x250 #define MSR_MTRRfix16K_80000 0x258 #define MSR_MTRRfix16K_A0000 0x259 @@ -353,6 +355,8 @@ #define MSR_MTRRdefType 0x2ff +#define MSR_MTRRdefType_Enable (1 << 11) + #define MSR_CORE_PERF_FIXED_CTR0 0x309 #define MSR_CORE_PERF_FIXED_CTR1 0x30a #define MSR_CORE_PERF_FIXED_CTR2 0x30b diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 097fe11..cb31338 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -79,6 +79,7 @@ static int lm_capable_kernel; static bool has_msr_hv_hypercall; static bool has_msr_hv_vapic; static bool has_msr_hv_tsc; +static bool has_msr_mtrr; static bool has_msr_architectural_pmu; static uint32_t num_architectural_pmu_counters; @@ -739,6 +740,10 @@ int kvm_arch_init_vcpu(CPUState *cs) env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave)); } + if (env->features[FEAT_1_EDX] & CPUID_MTRR) { + has_msr_mtrr = true; + } + return 0; } @@ -1183,7 +1188,7 @@ static int kvm_put_msrs(X86CPU *cpu, int level) CPUX86State *env = &cpu->env; struct { struct kvm_msrs info; - struct kvm_msr_entry entries[100]; + struct kvm_msr_entry entries[128]; } msr_data; struct kvm_msr_entry *msrs = msr_data.entries; int n = 0, i; @@ -1278,6 +1283,13 @@ static int kvm_put_msrs(X86CPU *cpu, int level) kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc); } + if (has_msr_mtrr) { + kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_deftype); + for (i = 0; i < MSR_MTRRcap_VCNT; i++) { + kvm_msr_entry_set(&msrs[n++], + MSR_MTRRphysMask(i), env->mtrr_var[i].mask); + } + } /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see * kvm_put_msr_feature_control. */