From patchwork Fri Apr 25 17:17:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin O'Connor X-Patchwork-Id: 342946 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 76D1A140157 for ; Sat, 26 Apr 2014 03:17:55 +1000 (EST) Received: from localhost ([::1]:59254 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wdjl3-0001Xc-1C for incoming@patchwork.ozlabs.org; Fri, 25 Apr 2014 13:17:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41789) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wdjke-0001D4-MY for qemu-devel@nongnu.org; Fri, 25 Apr 2014 13:17:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WdjkY-000276-E3 for qemu-devel@nongnu.org; Fri, 25 Apr 2014 13:17:28 -0400 Received: from mail-pb0-f48.google.com ([209.85.160.48]:46159) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WdjkY-00026u-80 for qemu-devel@nongnu.org; Fri, 25 Apr 2014 13:17:22 -0400 Received: by mail-pb0-f48.google.com with SMTP id md12so3421669pbc.7 for ; Fri, 25 Apr 2014 10:17:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:mime-version :content-type:content-disposition:user-agent; bh=tcqwOuIxaS/i02G2TSt5SQgQ6cf4aS0UvMKrdYHhNzc=; b=Algptht6Iq0VLktVOGgBRyp0bIrIok1VdWoD/koCxbJG5Mvsi0Ly6vc9KcYUD6xg24 dtGw1xzxxh8HPxLkD9LLXVdBM2O1jtO9YqYHpvOToB66sgCFBzlziW0CRdQN1SRCwHuC j7n9zYoXMaBPLykxjw5KOZRgey0sh/7YRw0Ne29tqrKmAVzsQjWPAurHA5G73z2XKStE fKo//wsuomH2IHNItqU+XltEVXaxFrlrPLdOFi5CrcUCUr+25KRu5zwDkbQuqKelVaBy jUiXYMbB3q2Fk9TQ5GdypEI4QPotqXVEgHKRnsQ7fk4Cp4hz3bVxL/i3R/JkB/97/6r4 G/tw== X-Gm-Message-State: ALoCoQnYo5repGXoepLDTE7mVnmBJrlqzzOoPQJ0fHfO1G0M0VhHGkbz2moBMl6QhfVV+Yc5IbBH X-Received: by 10.66.122.72 with SMTP id lq8mr9311834pab.69.1398446241175; Fri, 25 Apr 2014 10:17:21 -0700 (PDT) Received: from localhost (207-172-170-53.c3-0.avec-ubr1.nyr-avec.ny.cable.rcn.com. [207.172.170.53]) by mx.google.com with ESMTPSA id el14sm41398581pac.31.2014.04.25.10.17.19 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 25 Apr 2014 10:17:20 -0700 (PDT) Date: Fri, 25 Apr 2014 13:17:18 -0400 From: Kevin O'Connor To: qemu-devel@nongnu.org Message-ID: <20140425171718.GA1591@morn.localdomain> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.160.48 Cc: Gerd Hoffmann , Richard Henderson Subject: [Qemu-devel] [PATCH] SMI handler should set the CPL to zero and save and restore it on rsm. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The current SMI interrupt handler is being run with the same CPL as the code it interrupts. If the existing code is running with CPL=3, then the SMI handler can cause spurious exceptions. The System Management Mode (SMM) should always run at the highest protection level. Signed-off-by: Kevin O'Connor --- I'm not very familiar with the QEMU TCG code, so it is possible there is a better way to accomplish this. I can confirm that without this patch an extended SeaBIOS SMI handler can cause spurious faults, but it works correctly with this patch. --- target-i386/smm_helper.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c index 35901c9..ad5abf2 100644 --- a/target-i386/smm_helper.c +++ b/target-i386/smm_helper.c @@ -66,6 +66,7 @@ void do_smm_enter(X86CPU *cpu) stq_phys(cs->as, sm_state + offset + 8, dt->base); } + stw_phys(cs->as, sm_state + 0x7e62, env->hflags & HF_CPL_MASK); stq_phys(cs->as, sm_state + 0x7e68, env->gdt.base); stl_phys(cs->as, sm_state + 0x7e64, env->gdt.limit); @@ -134,6 +135,7 @@ void do_smm_enter(X86CPU *cpu) stl_phys(cs->as, sm_state + 0x7f74, env->gdt.base); stl_phys(cs->as, sm_state + 0x7f70, env->gdt.limit); + stw_phys(cs->as, sm_state + 0x7f6e, env->hflags & HF_CPL_MASK); stl_phys(cs->as, sm_state + 0x7f58, env->idt.base); stl_phys(cs->as, sm_state + 0x7f54, env->idt.limit); @@ -163,6 +165,7 @@ void do_smm_enter(X86CPU *cpu) cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); env->eip = 0x00008000; + cpu_x86_set_cpl(env, 0); cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase, 0xffffffff, 0); cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff, 0); @@ -201,6 +204,7 @@ void helper_rsm(CPUX86State *env) 0xf0ff) << 8); } + cpu_x86_set_cpl(env, lduw_phys(cs->as, sm_state + 0x7e62) & HF_CPL_MASK); env->gdt.base = ldq_phys(cs->as, sm_state + 0x7e68); env->gdt.limit = ldl_phys(cs->as, sm_state + 0x7e64); @@ -271,6 +275,7 @@ void helper_rsm(CPUX86State *env) env->gdt.base = ldl_phys(cs->as, sm_state + 0x7f74); env->gdt.limit = ldl_phys(cs->as, sm_state + 0x7f70); + cpu_x86_set_cpl(env, lduw_phys(cs->as, sm_state + 0x7f6e) & HF_CPL_MASK); env->idt.base = ldl_phys(cs->as, sm_state + 0x7f58); env->idt.limit = ldl_phys(cs->as, sm_state + 0x7f54);