From patchwork Mon Feb 17 13:22:43 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kurz X-Patchwork-Id: 320961 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id B89952C008F for ; Tue, 18 Feb 2014 00:23:50 +1100 (EST) Received: from localhost ([::1]:40449 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WFOAm-0007mg-8a for incoming@patchwork.ozlabs.org; Mon, 17 Feb 2014 08:23:48 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49224) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WFO9y-0007ZG-VR for qemu-devel@nongnu.org; Mon, 17 Feb 2014 08:23:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WFO9q-0001sB-1c for qemu-devel@nongnu.org; Mon, 17 Feb 2014 08:22:58 -0500 Received: from e06smtp17.uk.ibm.com ([195.75.94.113]:40401) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WFO9p-0001rs-Pz for qemu-devel@nongnu.org; Mon, 17 Feb 2014 08:22:49 -0500 Received: from /spool/local by e06smtp17.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 17 Feb 2014 13:22:49 -0000 Received: from d06dlp03.portsmouth.uk.ibm.com (9.149.20.15) by e06smtp17.uk.ibm.com (192.168.101.147) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Mon, 17 Feb 2014 13:22:46 -0000 Received: from b06cxnps3074.portsmouth.uk.ibm.com (d06relay09.portsmouth.uk.ibm.com [9.149.109.194]) by d06dlp03.portsmouth.uk.ibm.com (Postfix) with ESMTP id A65321B0806E; Mon, 17 Feb 2014 13:22:22 +0000 (GMT) Received: from d06av07.portsmouth.uk.ibm.com (d06av07.portsmouth.uk.ibm.com [9.149.37.248]) by b06cxnps3074.portsmouth.uk.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id s1HDMXM665929352; Mon, 17 Feb 2014 13:22:33 GMT Received: from d06av07.portsmouth.uk.ibm.com (localhost [127.0.0.1]) by d06av07.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id s1HDMjES027333; Mon, 17 Feb 2014 08:22:45 -0500 Received: from smtp.lab.toulouse-stg.fr.ibm.com (srv01.lab.toulouse-stg.fr.ibm.com [9.101.4.1]) by d06av07.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id s1HDMiWZ027328; Mon, 17 Feb 2014 08:22:45 -0500 Received: from bahia.local (icon-9-167-237-122.megacenter.de.ibm.com [9.167.237.122]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 11BD6210FFE; Mon, 17 Feb 2014 14:22:43 +0100 (CET) To: agraf@suse.de, aneesh.kumar@linux.vnet.ibm.com From: Greg Kurz Date: Mon, 17 Feb 2014 14:22:43 +0100 Message-ID: <20140217132242.25977.68875.stgit@bahia.local> In-Reply-To: <20140217132213.25977.96973.stgit@bahia.local> References: <20140217132213.25977.96973.stgit@bahia.local> User-Agent: StGit/0.16 MIME-Version: 1.0 X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14021713-0542-0000-0000-000008075994 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] X-Received-From: 195.75.94.113 Cc: paulus@samba.org, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH 4/4] target-ppc: Update ppc_hash64_store_hpte to support updating in-kernel htab X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Aneesh Kumar K.V This support updating htab managed by the hypervisor. Currently we don't have any user for this feature. This actually bring the store_hpte interface in-line with the load_hpte one. We may want to use this when we want to emulate henter hcall in qemu for HV kvm. [ folded fix for the "warn_unused_result" build break in kvmppc_hash64_write_pte(), Greg Kurz ] Signed-off-by: Aneesh Kumar K.V Signed-off-by: Greg Kurz Signed-off-by: Alexander Graf --- target-ppc/kvm.c | 36 ++++++++++++++++++++++++++++++++++++ target-ppc/kvm_ppc.h | 10 ++++++++++ target-ppc/mmu-hash64.c | 20 ++++++++++++++++++++ target-ppc/mmu-hash64.h | 17 ++--------------- 4 files changed, 68 insertions(+), 15 deletions(-) diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index e50a50e..84aa4e4 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -1991,3 +1991,39 @@ void kvmppc_hash64_free_pteg(uint64_t token) g_free(htab_buf); return; } + +void kvmppc_hash64_write_pte(CPUPPCState *env, target_ulong pte_index, + target_ulong pte0, target_ulong pte1) +{ + int htab_fd; + struct kvm_get_htab_fd ghf; + struct kvm_get_htab_buf hpte_buf; + + ghf.flags = 0; + ghf.start_index = 0; /* Ignored */ + htab_fd = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &ghf); + if (htab_fd < 0) { + goto error_out; + } + + hpte_buf.header.n_valid = 1; + hpte_buf.header.n_invalid = 0; + hpte_buf.header.index = pte_index; + hpte_buf.hpte[0] = pte0; + hpte_buf.hpte[1] = pte1; + /* + * Write the hpte entry. + * CAUTION: write() has the warn_unused_result attribute. Hence we + * need to check the return value, even though we do nothing. + */ + if (write(htab_fd, &hpte_buf, sizeof(hpte_buf)) < 0) { + goto out_close; + } + +out_close: + close(htab_fd); + return; + +error_out: + return; +} diff --git a/target-ppc/kvm_ppc.h b/target-ppc/kvm_ppc.h index 800e1ad..a65d345 100644 --- a/target-ppc/kvm_ppc.h +++ b/target-ppc/kvm_ppc.h @@ -47,6 +47,9 @@ int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index, uint64_t kvmppc_hash64_read_pteg(PowerPCCPU *cpu, target_ulong pte_index); void kvmppc_hash64_free_pteg(uint64_t token); +void kvmppc_hash64_write_pte(CPUPPCState *env, target_ulong pte_index, + target_ulong pte0, target_ulong pte1); + #else static inline uint32_t kvmppc_get_tbfreq(void) @@ -207,6 +210,13 @@ static inline void kvmppc_hash64_free_pteg(uint64_t token) abort(); } +static inline void kvmppc_hash64_write_pte(CPUPPCState *env, + target_ulong pte_index, + target_ulong pte0, target_ulong pte1) +{ + abort(); +} + #endif #ifndef CONFIG_KVM diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index 8dd5d22..f2af4fb 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -603,3 +603,23 @@ hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr) return ppc_hash64_pte_raddr(slb, pte, addr) & TARGET_PAGE_MASK; } + +void ppc_hash64_store_hpte(CPUPPCState *env, + target_ulong pte_index, + target_ulong pte0, target_ulong pte1) +{ + CPUState *cs = ENV_GET_CPU(env); + + if (kvmppc_kern_htab) { + return kvmppc_hash64_write_pte(env, pte_index, pte0, pte1); + } + + pte_index *= HASH_PTE_SIZE_64; + if (env->external_htab) { + stq_p(env->external_htab + pte_index, pte0); + stq_p(env->external_htab + pte_index + HASH_PTE_SIZE_64/2, pte1); + } else { + stq_phys(cs->as, env->htab_base + pte_index, pte0); + stq_phys(cs->as, env->htab_base + pte_index + HASH_PTE_SIZE_64/2, pte1); + } +} diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h index 49d866b..1746b3e 100644 --- a/target-ppc/mmu-hash64.h +++ b/target-ppc/mmu-hash64.h @@ -9,6 +9,8 @@ int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs); hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr); int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, int mmu_idx); +void ppc_hash64_store_hpte(CPUPPCState *env, target_ulong index, + target_ulong pte0, target_ulong pte1); #endif /* @@ -106,21 +108,6 @@ static inline target_ulong ppc_hash64_load_hpte1(CPUPPCState *env, } } -static inline void ppc_hash64_store_hpte(CPUPPCState *env, - target_ulong pte_index, - target_ulong pte0, target_ulong pte1) -{ - CPUState *cs = ENV_GET_CPU(env); - pte_index *= HASH_PTE_SIZE_64; - if (env->external_htab) { - stq_p(env->external_htab + pte_index, pte0); - stq_p(env->external_htab + pte_index + HASH_PTE_SIZE_64/2, pte1); - } else { - stq_phys(cs->as, env->htab_base + pte_index, pte0); - stq_phys(cs->as, env->htab_base + pte_index + HASH_PTE_SIZE_64/2, pte1); - } -} - typedef struct { uint64_t pte0, pte1; } ppc_hash_pte64_t;