From patchwork Thu Sep 5 22:28:17 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Williamson X-Patchwork-Id: 272989 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1ECEB2C00F1 for ; Fri, 6 Sep 2013 08:28:56 +1000 (EST) Received: from localhost ([::1]:34036 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VHi2o-0006VK-81 for incoming@patchwork.ozlabs.org; Thu, 05 Sep 2013 18:28:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48533) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VHi2L-0006My-5O for qemu-devel@nongnu.org; Thu, 05 Sep 2013 18:28:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VHi2E-0003Mf-VL for qemu-devel@nongnu.org; Thu, 05 Sep 2013 18:28:25 -0400 Received: from mx1.redhat.com ([209.132.183.28]:39179) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VHi2E-0003Mb-NF for qemu-devel@nongnu.org; Thu, 05 Sep 2013 18:28:18 -0400 Received: from int-mx02.intmail.prod.int.phx2.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id r85MSIF7021882 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Thu, 5 Sep 2013 18:28:18 -0400 Received: from bling.home (ovpn-113-59.phx2.redhat.com [10.3.113.59]) by int-mx02.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id r85MSHRN007691; Thu, 5 Sep 2013 18:28:17 -0400 To: alex.williamson@redhat.com From: Alex Williamson Date: Thu, 05 Sep 2013 16:28:17 -0600 Message-ID: <20130905222753.4024.46981.stgit@bling.home> User-Agent: StGit/0.16 MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.67 on 10.5.11.12 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH] vfio-pci: Test device reset capabilities X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Not all resets are created equal. PM reset is not very reliable, especially for GPUs, so we might want to opt for a bus reset if a standard reset will only do a D3hot->D0 transition. We can also use this to tell if the standard reset will do a bus reset (if neither has_pm_reset or has_flr is probed, but the device still supports reset). Signed-off-by: Alex Williamson --- hw/misc/vfio.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/hw/misc/vfio.c b/hw/misc/vfio.c index 75a53e2..ede026d 100644 --- a/hw/misc/vfio.c +++ b/hw/misc/vfio.c @@ -185,6 +185,8 @@ typedef struct VFIODevice { bool reset_works; bool has_vga; bool pci_aer; + bool has_flr; + bool has_pm_reset; } VFIODevice; typedef struct VFIOGroup { @@ -2513,6 +2515,42 @@ static int vfio_setup_pcie_cap(VFIODevice *vdev, int pos, uint8_t size) return pos; } +static void vfio_check_pcie_flr(VFIODevice *vdev, uint8_t pos) +{ + uint32_t cap = pci_get_long(vdev->pdev.config + pos + PCI_EXP_DEVCAP); + + if (cap & PCI_EXP_DEVCAP_FLR) { + DPRINTF("%04x:%02x:%02x.%x Supports FLR via PCIe cap\n", + vdev->host.domain, vdev->host.bus, vdev->host.slot, + vdev->host.function); + vdev->has_flr = true; + } +} + +static void vfio_check_pm_reset(VFIODevice *vdev, uint8_t pos) +{ + uint16_t csr = pci_get_word(vdev->pdev.config + pos + PCI_PM_CTRL); + + if (!(csr & PCI_PM_CTRL_NO_SOFT_RESET)) { + DPRINTF("%04x:%02x:%02x.%x Supports PM reset\n", + vdev->host.domain, vdev->host.bus, vdev->host.slot, + vdev->host.function); + vdev->has_pm_reset = true; + } +} + +static void vfio_check_af_flr(VFIODevice *vdev, uint8_t pos) +{ + uint8_t cap = pci_get_byte(vdev->pdev.config + pos + PCI_AF_CAP); + + if ((cap & PCI_AF_CAP_TP) && (cap & PCI_AF_CAP_FLR)) { + DPRINTF("%04x:%02x:%02x.%x Supports FLR via AF cap\n", + vdev->host.domain, vdev->host.bus, vdev->host.slot, + vdev->host.function); + vdev->has_flr = true; + } +} + static int vfio_add_std_cap(VFIODevice *vdev, uint8_t pos) { PCIDevice *pdev = &vdev->pdev; @@ -2557,13 +2595,21 @@ static int vfio_add_std_cap(VFIODevice *vdev, uint8_t pos) ret = vfio_setup_msi(vdev, pos); break; case PCI_CAP_ID_EXP: + vfio_check_pcie_flr(vdev, pos); ret = vfio_setup_pcie_cap(vdev, pos, size); break; case PCI_CAP_ID_MSIX: ret = vfio_setup_msix(vdev, pos); break; case PCI_CAP_ID_PM: + vfio_check_pm_reset(vdev, pos); vdev->pm_cap = pos; + ret = pci_add_capability(pdev, cap_id, pos, size); + break; + case PCI_CAP_ID_AF: + vfio_check_af_flr(vdev, pos); + ret = pci_add_capability(pdev, cap_id, pos, size); + break; default: ret = pci_add_capability(pdev, cap_id, pos, size); break;