Message ID | 20130426211728.GC25132@hall.aurel32.net |
---|---|
State | New |
Headers | show |
Am 26.04.2013 um 23:17 schrieb Aurelien Jarno <aurelien@aurel32.net>: > On Fri, Apr 26, 2013 at 11:03:12PM +0200, Alexander Graf wrote: >> >> >> Am 26.04.2013 um 22:09 schrieb Blue Swirl <blauwirbel@gmail.com>: >> >>> On Fri, Apr 26, 2013 at 6:21 PM, Alexander Graf <agraf@suse.de> wrote: >>>> Hi Blue / Aurelien, >>>> >>>> This is my current patch queue for ppc. Please pull. >>> >>> Does not build with --enable-debug: >>> CC ppc-softmmu/target-ppc/translate.o >>> /src/qemu/target-ppc/translate.c: In function 'gen_lfiwax': >>> /src/qemu/target-ppc/translate.c:3378:5: error: incompatible type for >>> argument 2 of 'gen_qemu_ld32s' >>> /src/qemu/target-ppc/translate.c:2554:20: note: expected 'TCGv_i32' >>> but argument is of type 'TCGv_i64' >> >> I pushed an updated, fixed tree. > > Thanks, and sorry about that. Would it be possible to use the following > patch instead? It generates slightly better code (by folding the sign > extension in the load when possible). How about you just apply the pull request, diff your version against what's in there and apply the diff on top :). I'm quite sure that makes everyone's life easier ;). Alex > > > > target-ppc: emulate lfiwax instruction > > Needed for Power ISA version 2.05 compliance. > > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> > --- > target-ppc/translate.c | 22 ++++++++++++++++++++-- > 1 file changed, 20 insertions(+), 2 deletions(-) > > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index 1989818..b883a57 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -2531,7 +2531,6 @@ static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) > } > } > > -#if defined(TARGET_PPC64) > static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) > { > if (unlikely(ctx->le_mode)) { > @@ -2541,7 +2540,6 @@ static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) > } else > tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx); > } > -#endif > > static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) > { > @@ -3300,6 +3298,25 @@ GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT); > /* lfs lfsu lfsux lfsx */ > GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT); > > +/* lfiwax */ > +static void gen_lfiwax(DisasContext *ctx) > +{ > + TCGv EA; > + TCGv t0; > + if (unlikely(!ctx->fpu_enabled)) { > + gen_exception(ctx, POWERPC_EXCP_FPU); > + return; > + } > + gen_set_access_type(ctx, ACCESS_FLOAT); > + EA = tcg_temp_new(); > + t0 = tcg_temp_new(); > + gen_addr_reg_index(ctx, EA); > + gen_qemu_ld32s(ctx, t0, EA); > + tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0); > + tcg_temp_free(EA); > + tcg_temp_free(t0); > +} > + > /*** Floating-point store ***/ > #define GEN_STF(name, stop, opc, type) \ > static void glue(gen_, name)(DisasContext *ctx) \ > @@ -9014,6 +9031,7 @@ GEN_LDXF(name, ldop, 0x17, op | 0x00, type) > > GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT) > GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT) > +GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205), > > #undef GEN_STF > #undef GEN_STUF > -- > 1.7.10.4 > > > -- > Aurelien Jarno GPG: 1024D/F1BCDB73 > aurelien@aurel32.net http://www.aurel32.net
On Fri, Apr 26, 2013 at 11:42:19PM +0200, Alexander Graf wrote: > > > Am 26.04.2013 um 23:17 schrieb Aurelien Jarno <aurelien@aurel32.net>: > > > On Fri, Apr 26, 2013 at 11:03:12PM +0200, Alexander Graf wrote: > >> > >> > >> Am 26.04.2013 um 22:09 schrieb Blue Swirl <blauwirbel@gmail.com>: > >> > >>> On Fri, Apr 26, 2013 at 6:21 PM, Alexander Graf <agraf@suse.de> wrote: > >>>> Hi Blue / Aurelien, > >>>> > >>>> This is my current patch queue for ppc. Please pull. > >>> > >>> Does not build with --enable-debug: > >>> CC ppc-softmmu/target-ppc/translate.o > >>> /src/qemu/target-ppc/translate.c: In function 'gen_lfiwax': > >>> /src/qemu/target-ppc/translate.c:3378:5: error: incompatible type for > >>> argument 2 of 'gen_qemu_ld32s' > >>> /src/qemu/target-ppc/translate.c:2554:20: note: expected 'TCGv_i32' > >>> but argument is of type 'TCGv_i64' > >> > >> I pushed an updated, fixed tree. > > > > Thanks, and sorry about that. Would it be possible to use the following > > patch instead? It generates slightly better code (by folding the sign > > extension in the load when possible). > > How about you just apply the pull request, diff your version against what's in there and apply the diff on top :). This considered as an abuse of my commit powers and usually leads to complains. > I'm quite sure that makes everyone's life easier ;). Done anyway, I hope you won't complain ;) Aurelien
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 1989818..b883a57 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2531,7 +2531,6 @@ static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) } } -#if defined(TARGET_PPC64) static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) { if (unlikely(ctx->le_mode)) { @@ -2541,7 +2540,6 @@ static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) } else tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx); } -#endif static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) { @@ -3300,6 +3298,25 @@ GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT); /* lfs lfsu lfsux lfsx */ GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT); +/* lfiwax */ +static void gen_lfiwax(DisasContext *ctx) +{ + TCGv EA; + TCGv t0; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + gen_set_access_type(ctx, ACCESS_FLOAT); + EA = tcg_temp_new(); + t0 = tcg_temp_new(); + gen_addr_reg_index(ctx, EA); + gen_qemu_ld32s(ctx, t0, EA); + tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0); + tcg_temp_free(EA); + tcg_temp_free(t0); +} + /*** Floating-point store ***/ #define GEN_STF(name, stop, opc, type) \ static void glue(gen_, name)(DisasContext *ctx) \ @@ -9014,6 +9031,7 @@ GEN_LDXF(name, ldop, 0x17, op | 0x00, type) GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT) GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT) +GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205), #undef GEN_STF #undef GEN_STUF