From patchwork Tue Sep 25 22:48:41 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 186911 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 9B7E52C008A for ; Wed, 26 Sep 2012 08:48:57 +1000 (EST) Received: from localhost ([::1]:51814 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TGdvz-0007zt-Sd for incoming@patchwork.ozlabs.org; Tue, 25 Sep 2012 18:48:55 -0400 Received: from eggs.gnu.org ([208.118.235.92]:47769) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TGdvq-0007zL-FX for qemu-devel@nongnu.org; Tue, 25 Sep 2012 18:48:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TGdvp-0004do-3x for qemu-devel@nongnu.org; Tue, 25 Sep 2012 18:48:46 -0400 Received: from hall.aurel32.net ([88.191.126.93]:45414) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TGdvo-0004dU-U0 for qemu-devel@nongnu.org; Tue, 25 Sep 2012 18:48:45 -0400 Received: from [2001:470:d4ed:0:ea11:32ff:fea1:831a] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1TGdvm-0007Zu-N0; Wed, 26 Sep 2012 00:48:42 +0200 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1TGdvl-0003Wu-Jy; Wed, 26 Sep 2012 00:48:41 +0200 Date: Wed, 26 Sep 2012 00:48:41 +0200 From: Aurelien Jarno To: Richard Henderson Message-ID: <20120925224841.GJ23819@ohm.aurel32.net> References: <1348247620-12734-1-git-send-email-rth@twiddle.net> <1348247620-12734-4-git-send-email-rth@twiddle.net> <5060D693.7060601@twiddle.net> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <5060D693.7060601@twiddle.net> X-Mailer: Mutt 1.5.21 (2010-09-15) User-Agent: Mutt/1.5.21 (2010-09-15) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 88.191.126.93 Cc: Alex Barcelo , qemu-devel@nongnu.org Subject: Re: [Qemu-devel] [PATCH 3/7] tcg-i386: Implement movcond X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On Mon, Sep 24, 2012 at 02:54:27PM -0700, Richard Henderson wrote: > On 09/24/2012 02:37 PM, Alex Barcelo wrote: > > just finished a git-bisect and I found this... and now I do not fully > > understand why I have the problem. > > > > To replicate the error (in a i386 machine, at least): > > $ make clean && ./configure --enable-debug && make -j && make install > > [Note: I tried both ppc and i386 targets, so doesn't seem machine-dependent] > > $ ./path/to/qemu/bin/qemu-i386 doesntmatter > > Invalid op definition for movcond_i32 > > /mnt/DATA/DARCO/qemu-git/tcg/tcg.c:1170: tcg fatal error > > Aborted > > Ah, right. I only tried with -march=i686. > > >> + { INDEX_op_movcond_i32, { "r", "r", "ri", "r", "0" } }, > > Should be protected by > > #if TCG_TARGET_HAS_movcond_i32 > > If no one beats me to this, I'll submit a patch this evening. > > I have applied the following patch to fix the issue. commit f813cb838f19ee8637d3c365659e6a6bb0c9c974 Author: Aurelien Jarno Date: Wed Sep 26 00:30:12 2012 +0200 tcg/i386: fix build with -march < i686 The movcond_i32 op has to be protected with TCG_TARGET_HAS_movcond_i32 to fix the build with -march < i686. Thanks to Richard Henderson for the hint. Reported-by: Alex Barcelo Signed-off-by: Aurelien Jarno diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c index 122d636..0e218c8 100644 --- a/tcg/i386/tcg-target.c +++ b/tcg/i386/tcg-target.c @@ -1893,7 +1893,9 @@ static const TCGTargetOpDef x86_op_defs[] = { { INDEX_op_setcond_i32, { "q", "r", "ri" } }, { INDEX_op_deposit_i32, { "Q", "0", "Q" } }, +#if TCG_TARGET_HAS_movcond_i32 { INDEX_op_movcond_i32, { "r", "r", "ri", "r", "0" } }, +#endif #if TCG_TARGET_REG_BITS == 32 { INDEX_op_mulu2_i32, { "a", "d", "a", "r" } },