From patchwork Mon Sep 24 15:27:20 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasilis Liaskovitis X-Patchwork-Id: 186464 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D0C032C0080 for ; Tue, 25 Sep 2012 01:27:47 +1000 (EST) Received: from localhost ([::1]:45223 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TGAZV-0001UK-Vr for incoming@patchwork.ozlabs.org; Mon, 24 Sep 2012 11:27:45 -0400 Received: from eggs.gnu.org ([208.118.235.92]:41619) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TGAZL-0001T1-QG for qemu-devel@nongnu.org; Mon, 24 Sep 2012 11:27:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TGAZB-0005Hx-UJ for qemu-devel@nongnu.org; Mon, 24 Sep 2012 11:27:35 -0400 Received: from mail-bk0-f45.google.com ([209.85.214.45]:38178) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TGAZB-0005Hs-Jr for qemu-devel@nongnu.org; Mon, 24 Sep 2012 11:27:25 -0400 Received: by bkcjg9 with SMTP id jg9so2414772bkc.4 for ; Mon, 24 Sep 2012 08:27:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent :x-gm-message-state; bh=1p/KyQWsewSTjpJ0DrP4sZzzYH9UiRxxK5m5Ze7Qat4=; b=BKfNzNYUluoxqBaQ5iO6L0dt7xqroN3jwqV49K3fOX5lQF9KjSs5JwLmSwnqrl4HKm y+khepeQQs5Kw7ouuH1NKs0oMCJpCwHNnV0xQDmueArJ4dhcHacJ2CWSS5tSVj0n5Imv eTgy9+YUHTm5n2vlP4seNS/4S9bCWlylqCnNehuIR+zaZaVE/CNi78TjC4qQJ9EEauW6 b4tgibydK9mf1qfqIty1hgFytHcPFY5BgikLVZx1CwWNROKcMkHooXuF/nnvqrVcIYV0 lfqsZQQx4Uv3P+vUpNqXnDCDrlUiIdyFNc1zoUGDSgBl0EvSxt9Qbbi2SXv/BMcIgzkK 3QBg== Received: by 10.204.129.16 with SMTP id m16mr4826577bks.136.1348500444070; Mon, 24 Sep 2012 08:27:24 -0700 (PDT) Received: from dhcp-192-168-178-175.profitbricks.localdomain ([62.217.45.26]) by mx.google.com with ESMTPS id gy18sm2110217bkc.4.2012.09.24.08.27.23 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 24 Sep 2012 08:27:23 -0700 (PDT) Date: Mon, 24 Sep 2012 17:27:20 +0200 From: Vasilis Liaskovitis To: Blue Swirl Message-ID: <20120924152720.GD4457@dhcp-192-168-178-175.profitbricks.localdomain> References: <1348226255-4226-1-git-send-email-vasilis.liaskovitis@profitbricks.com> <1348226255-4226-9-git-send-email-vasilis.liaskovitis@profitbricks.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-Gm-Message-State: ALoCoQkqSBAf6oiIx23uCyYBQZ3ZOyxvgat7LPlXpHjQsaY3dEQKc64p9XWsH/pGyS8b/faioy/3 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.214.45 Cc: kvm@vger.kernel.org, seabios@seabios.org, qemu-devel@nongnu.org, gleb@redhat.com, kevin@koconnor.net, avi@redhat.com, anthony@codemonkey.ws, imammedo@redhat.com, eblake@redhat.com, kraxel@redhat.com Subject: Re: [Qemu-devel] [RFC PATCH v3 08/19] pc: calculate dimm physical addresses and adjust memory map X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On Sat, Sep 22, 2012 at 02:15:28PM +0000, Blue Swirl wrote: > > + > > +/* Function to configure memory offsets of hotpluggable dimms */ > > + > > +target_phys_addr_t pc_set_hp_memory_offset(uint64_t size) > > +{ > > + target_phys_addr_t ret; > > + > > + /* on first call, initialize ram_hp_offset */ > > + if (!ram_hp_offset) { > > + if (ram_size >= PCI_HOLE_START ) { > > + ram_hp_offset = 0x100000000LL + (ram_size - PCI_HOLE_START); > > + } else { > > + ram_hp_offset = ram_size; > > + } > > + } > > + > > + if (ram_hp_offset >= 0x100000000LL) { > > + ret = ram_hp_offset; > > + above_4g_hp_mem_size += size; > > + ram_hp_offset += size; > > + } > > + /* if dimm fits before pci hole, append it normally */ > > + else if (ram_hp_offset + size <= PCI_HOLE_START) { > > } else if ... > > > + ret = ram_hp_offset; > > + below_4g_hp_mem_size += size; > > + ram_hp_offset += size; > > + } > > + /* otherwise place it above 4GB */ > > + else { > > } else { > > > + ret = 0x100000000LL; > > + above_4g_hp_mem_size += size; > > + ram_hp_offset = 0x100000000LL + size; > > + } > > + > > + return ret; > > +} > > But the function and use of lots of global variables is ugly. The dimm > devices should be just created in piix_pci.c (i440fx) directly with > correct offsets and sizes, so all below_4g_mem_size etc. calculations > should be moved there. That would implement the PMC part of i440fx. > > For ISA PC, probably the board should create the DIMMs since there may > not be a memory controller. The >4G logic does not make sense there > anyway. What about moving the implementation to pc_piix.c? Initial RAM and pci windows are already calculated in pc_init1, and then passed to i440fx_init. The memory bus could be attached to i440fx for pci-enabled pc and to isabus-bridge for isa-pc (isa-pc not tested yet). Something like the following: --- hw/pc.h | 1 + hw/pc_piix.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++------ 2 files changed, 52 insertions(+), 6 deletions(-) diff --git a/hw/pc.h b/hw/pc.h index e4db071..d6cc43b 100644 --- a/hw/pc.h +++ b/hw/pc.h @@ -10,6 +10,7 @@ #include "memory.h" #include "ioapic.h" +#define PCI_HOLE_START 0xe0000000 /* PC-style peripherals (also used by other machines). */ /* serial.c */ diff --git a/hw/pc_piix.c b/hw/pc_piix.c index 88ff041..17db95a 100644 --- a/hw/pc_piix.c +++ b/hw/pc_piix.c @@ -43,6 +43,7 @@ #include "xen.h" #include "memory.h" #include "exec-memory.h" +#include "dimm.h" #ifdef CONFIG_XEN # include #endif @@ -52,6 +53,8 @@ static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 }; static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 }; static const int ide_irq[MAX_IDE_BUS] = { 14, 15 }; +static ram_addr_t below_4g_hp_mem_size = 0; +static ram_addr_t above_4g_hp_mem_size = 0; static void kvm_piix3_setup_irq_routing(bool pci_enabled) { @@ -117,6 +120,41 @@ static void ioapic_init(GSIState *gsi_state) } } +static target_phys_addr_t pc_set_hp_memory_offset(uint64_t size) +{ + target_phys_addr_t ret; + static ram_addr_t ram_hp_offset = 0; + + /* on first call, initialize ram_hp_offset */ + if (!ram_hp_offset) { + if (ram_size >= PCI_HOLE_START ) { + ram_hp_offset = 0x100000000LL + (ram_size - PCI_HOLE_START); + } else { + ram_hp_offset = ram_size; + } + } + + if (ram_hp_offset >= 0x100000000LL) { + ret = ram_hp_offset; + above_4g_hp_mem_size += size; + ram_hp_offset += size; + } + /* if dimm fits before pci hole, append it normally */ + else if (ram_hp_offset + size <= PCI_HOLE_START) { + ret = ram_hp_offset; + below_4g_hp_mem_size += size; + ram_hp_offset += size; + } + /* otherwise place it above 4GB */ + else { + ret = 0x100000000LL; + above_4g_hp_mem_size += size; + ram_hp_offset = 0x100000000LL + size; + } + + return ret; +} + /* PC hardware initialisation */ static void pc_init1(MemoryRegion *system_memory, MemoryRegion *system_io, @@ -155,9 +193,9 @@ static void pc_init1(MemoryRegion *system_memory, kvmclock_create(); } - if (ram_size >= 0xe0000000 ) { - above_4g_mem_size = ram_size - 0xe0000000; - below_4g_mem_size = 0xe0000000; + if (ram_size >= PCI_HOLE_START ) { + above_4g_mem_size = ram_size - PCI_HOLE_START; + below_4g_mem_size = PCI_HOLE_START; } else { above_4g_mem_size = 0; below_4g_mem_size = ram_size; @@ -172,6 +210,9 @@ static void pc_init1(MemoryRegion *system_memory, rom_memory = system_memory; } + /* adjust memory map for hotplug dimms */ + dimm_calc_offsets(pc_set_hp_memory_offset); + /* allocate ram and load rom/bios */ if (!xen_enabled()) { fw_cfg = pc_memory_init(system_memory, @@ -192,18 +233,22 @@ static void pc_init1(MemoryRegion *system_memory, if (pci_enabled) { pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, &isa_bus, gsi, system_memory, system_io, ram_size, - below_4g_mem_size, - 0x100000000ULL - below_4g_mem_size, - 0x100000000ULL + above_4g_mem_size, + below_4g_mem_size + below_4g_hp_mem_size, + 0x100000000ULL - below_4g_mem_size + - below_4g_hp_mem_size, + 0x100000000ULL + above_4g_mem_size + + above_4g_hp_mem_size, (sizeof(target_phys_addr_t) == 4 ? 0 : ((uint64_t)1 << 62)), pci_memory, ram_memory); + main_memory_bus_create(object_resolve_path("i440fx", NULL)); } else { pci_bus = NULL; i440fx_state = NULL; isa_bus = isa_bus_new(NULL, system_io); no_hpet = 1; + main_memory_bus_create(object_resolve_path("isabus-bridge", NULL)); } isa_bus_irqs(isa_bus, gsi);