@@ -26,3 +26,12 @@ Entry max_cpus+nb_numa_nodes+1 contains the number of memory dimms (nb_hp_dimms)
The last 3 * nb_hp_dimms entries are organized in triplets: Each triplet contains
the physical address offset, size (in bytes), and node proximity for the
respective dimm.
+
+FW_CFG_PCI_WINDOW paravirt info
+--------------------
+QEMU passes the starting address for the 32-bit and 64-bit PCI windows to BIOS.
+The following layouts are followed:
+
+--------------------------------
+pcimem32_start | pcimem64_start |
+--------------------------------
@@ -27,6 +27,7 @@
#define FW_CFG_SETUP_SIZE 0x17
#define FW_CFG_SETUP_DATA 0x18
#define FW_CFG_FILE_DIR 0x19
+#define FW_CFG_PCI_WINDOW 0x1a
#define FW_CFG_FILE_FIRST 0x20
#define FW_CFG_FILE_SLOTS 0x10
@@ -44,6 +44,7 @@
#include "memory.h"
#include "exec-memory.h"
#include "dimm.h"
+#include "fw_cfg.h"
#ifdef CONFIG_XEN
# include <xen/hvm/hvm_info_table.h>
#endif
@@ -149,6 +150,7 @@ static void pc_init1(MemoryRegion *system_memory,
MemoryRegion *pci_memory;
MemoryRegion *rom_memory;
void *fw_cfg = NULL;
+ uint64_t *pci_window_fw_cfg;
pc_cpus_init(cpu_model);
@@ -205,6 +207,14 @@ static void pc_init1(MemoryRegion *system_memory,
? 0
: ((uint64_t)1 << 62)),
pci_memory, ram_memory);
+
+ pci_window_fw_cfg = g_malloc0(2 * 8);
+ pci_window_fw_cfg[0] = cpu_to_le64(below_4g_mem_size +
+ below_4g_hp_mem_size);
+ pci_window_fw_cfg[1] = cpu_to_le64(0x100000000ULL + above_4g_mem_size
+ + above_4g_hp_mem_size);
+ fw_cfg_add_bytes(fw_cfg, FW_CFG_PCI_WINDOW,
+ (uint8_t *)pci_window_fw_cfg, 2 * 8);
} else {
pci_bus = NULL;
i440fx_state = NULL;
Qemu already calculates the 32-bit and 64-bit PCI starting offsets based on initial memory and hotplug-able dimms. This info needs to be passed to Seabios for PCI initialization. Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis@profitbricks.com> --- docs/specs/fwcfg.txt | 9 +++++++++ hw/fw_cfg.h | 1 + hw/pc_piix.c | 10 ++++++++++ 3 files changed, 20 insertions(+), 0 deletions(-)