From patchwork Thu Apr 5 05:51:06 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Williamson X-Patchwork-Id: 150870 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id EB214B7047 for ; Thu, 5 Apr 2012 16:06:20 +1000 (EST) Received: from localhost ([::1]:51856 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SFfbZ-0006yV-SU for incoming@patchwork.ozlabs.org; Thu, 05 Apr 2012 01:51:33 -0400 Received: from eggs.gnu.org ([208.118.235.92]:44488) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SFfbN-0006nN-Ar for qemu-devel@nongnu.org; Thu, 05 Apr 2012 01:51:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SFfbL-000297-9o for qemu-devel@nongnu.org; Thu, 05 Apr 2012 01:51:20 -0400 Received: from mx1.redhat.com ([209.132.183.28]:35874) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SFfbL-00028x-1r for qemu-devel@nongnu.org; Thu, 05 Apr 2012 01:51:19 -0400 Received: from int-mx02.intmail.prod.int.phx2.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q355p8RC017070 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Thu, 5 Apr 2012 01:51:08 -0400 Received: from bling.home (ovpn-113-138.phx2.redhat.com [10.3.113.138]) by int-mx02.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id q355p7lA012663; Thu, 5 Apr 2012 01:51:07 -0400 From: Alex Williamson To: qemu-devel@nongnu.org, mst@redhat.com Date: Wed, 04 Apr 2012 23:51:06 -0600 Message-ID: <20120405055106.31461.82682.stgit@bling.home> In-Reply-To: <20120405050848.31461.10826.stgit@bling.home> References: <20120405050848.31461.10826.stgit@bling.home> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.67 on 10.5.11.12 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.132.183.28 Cc: aliguori@us.ibm.com, gleb@redhat.com, jbaron@redhat.com, yamahata@valinux.co.jp, alex.williamson@redhat.com, kraxel@redhat.com, pbonzini@redhat.com, imammedo@redhat.com, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 1/5] acpi_piix4: Disallow write to up/down PCI hotplug registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org These are never written, clarify spec, remove access. Split reads into two smaller functions. Signed-off-by: Alex Williamson --- docs/specs/acpi_pci_hotplug.txt | 4 ++-- hw/acpi_piix4.c | 42 ++++++++++++--------------------------- 2 files changed, 15 insertions(+), 31 deletions(-) diff --git a/docs/specs/acpi_pci_hotplug.txt b/docs/specs/acpi_pci_hotplug.txt index f0f74a7..1e2c8a2 100644 --- a/docs/specs/acpi_pci_hotplug.txt +++ b/docs/specs/acpi_pci_hotplug.txt @@ -15,14 +15,14 @@ PCI slot injection notification pending (IO port 0xae00-0xae03, 4-byte access): Slot injection notification pending. One bit per slot. Read by ACPI BIOS GPE.1 handler to notify OS of injection -events. +events. Read-only. PCI slot removal notification (IO port 0xae04-0xae07, 4-byte access): ----------------------------------------------------- Slot removal notification pending. One bit per slot. Read by ACPI BIOS GPE.1 handler to notify OS of removal -events. +events. Read-only. PCI device eject (IO port 0xae08-0xae0b, 4-byte access): ---------------------------------------- diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c index 0c77730..44d1423 100644 --- a/hw/acpi_piix4.c +++ b/hw/acpi_piix4.c @@ -41,7 +41,8 @@ #define GPE_BASE 0xafe0 #define PROC_BASE 0xaf00 #define GPE_LEN 4 -#define PCI_BASE 0xae00 +#define PCI_UP_BASE 0xae00 +#define PCI_DOWN_BASE 0xae04 #define PCI_EJ_BASE 0xae08 #define PCI_RMV_BASE 0xae0c @@ -468,38 +469,22 @@ static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val); } -static uint32_t pcihotplug_read(void *opaque, uint32_t addr) +static uint32_t pci_up_read(void *opaque, uint32_t addr) { - uint32_t val = 0; - struct pci_status *g = opaque; - switch (addr) { - case PCI_BASE: - val = g->up; - break; - case PCI_BASE + 4: - val = g->down; - break; - default: - break; - } + PIIX4PMState *s = opaque; + uint32_t val = s->pci0_status.up; - PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val); + PIIX4_DPRINTF("pci_up_read %x\n", val); return val; } -static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val) +static uint32_t pci_down_read(void *opaque, uint32_t addr) { - struct pci_status *g = opaque; - switch (addr) { - case PCI_BASE: - g->up = val; - break; - case PCI_BASE + 4: - g->down = val; - break; - } + PIIX4PMState *s = opaque; + uint32_t val = s->pci0_status.down; - PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val); + PIIX4_DPRINTF("pci_down_read %x\n", val); + return val; } static uint32_t pciej_read(void *opaque, uint32_t addr) @@ -545,7 +530,6 @@ static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) { - struct pci_status *pci0_status = &s->pci0_status; int i = 0, cpus = smp_cpus; while (cpus > 0) { @@ -560,8 +544,8 @@ static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) register_ioport_write(PROC_BASE, 32, 1, gpe_writeb, s); register_ioport_read(PROC_BASE, 32, 1, gpe_readb, s); - register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status); - register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, pci0_status); + register_ioport_read(PCI_UP_BASE, 4, 4, pci_up_read, s); + register_ioport_read(PCI_DOWN_BASE, 4, 4, pci_down_read, s); register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus); register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, bus);