From patchwork Wed Mar 7 00:14:13 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Williamson X-Patchwork-Id: 145115 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A9383B6EEC for ; Wed, 7 Mar 2012 11:14:28 +1100 (EST) Received: from localhost ([::1]:53970 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S54WQ-0004W7-C7 for incoming@patchwork.ozlabs.org; Tue, 06 Mar 2012 19:14:26 -0500 Received: from eggs.gnu.org ([208.118.235.92]:43049) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S54WH-0004W0-G9 for qemu-devel@nongnu.org; Tue, 06 Mar 2012 19:14:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S54WF-0005UQ-RB for qemu-devel@nongnu.org; Tue, 06 Mar 2012 19:14:17 -0500 Received: from mx1.redhat.com ([209.132.183.28]:6959) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S54WF-0005UM-IZ for qemu-devel@nongnu.org; Tue, 06 Mar 2012 19:14:15 -0500 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q270EEVb012561 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Tue, 6 Mar 2012 19:14:14 -0500 Received: from bling.home ([10.3.113.14]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id q270EDr5021598; Tue, 6 Mar 2012 19:14:13 -0500 From: Alex Williamson To: qemu-devel@nongnu.org Date: Tue, 06 Mar 2012 17:14:13 -0700 Message-ID: <20120307001405.3079.50312.stgit@bling.home> In-Reply-To: <20120307000340.3079.87515.stgit@bling.home> References: <20120307000340.3079.87515.stgit@bling.home> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.132.183.28 Cc: alex.williamson@redhat.com, ddutile@redhat.com, gleb@redhat.com, mst@redhat.com Subject: [Qemu-devel] [PATCH 2/6] acpi_piix4: Only allow writes to PCI hotplug eject register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This is never read. We can also derive bus from the write handler, which later makes this easier to call directly. Note that pciej_write was actually called with (PCIBus *)dev->bus, which is cast as a void* allowing us to pretend it's a BusState*. Fix this so we don't depend on the BusState location within PCIBus. Signed-off-by: Alex Williamson --- hw/acpi_piix4.c | 13 ++++--------- 1 files changed, 4 insertions(+), 9 deletions(-) diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c index 5960b7f..4d88e23 100644 --- a/hw/acpi_piix4.c +++ b/hw/acpi_piix4.c @@ -489,15 +489,11 @@ static uint32_t pci_updown_read(void *opaque, uint32_t addr) return val; } -static uint32_t pciej_read(void *opaque, uint32_t addr) -{ - PIIX4_DPRINTF("pciej read %x\n", addr); - return 0; -} - static void pciej_write(void *opaque, uint32_t addr, uint32_t val) { - BusState *bus = opaque; + PIIX4PMState *s = opaque; + PCIDevice *dev = &s->dev; + BusState *bus = qdev_get_parent_bus(&dev->qdev); DeviceState *qdev, *next; int slot = ffs(val) - 1; @@ -548,8 +544,7 @@ static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) register_ioport_read(PCI_UP_BASE, 8, 4, pci_updown_read, s); - register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus); - register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, bus); + register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, s); register_ioport_write(PCI_RMV_BASE, 4, 4, pcirmv_write, s); register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s);