From patchwork Fri Jan 13 16:07:06 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 135913 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8534BB6F65 for ; Sat, 14 Jan 2012 03:07:29 +1100 (EST) Received: from localhost ([::1]:44643 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rljf5-00010z-Eu for incoming@patchwork.ozlabs.org; Fri, 13 Jan 2012 11:07:27 -0500 Received: from eggs.gnu.org ([140.186.70.92]:37231) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rljey-00010r-N4 for qemu-devel@nongnu.org; Fri, 13 Jan 2012 11:07:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rljex-0003UX-Ic for qemu-devel@nongnu.org; Fri, 13 Jan 2012 11:07:20 -0500 Received: from hall.aurel32.net ([88.191.126.93]:35244) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rljex-0003U7-6D; Fri, 13 Jan 2012 11:07:19 -0500 Received: from [2001:470:d4ed:0:5e26:aff:fe2b:6f5b] (helo=volta.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Rljem-0006UL-4v; Fri, 13 Jan 2012 17:07:08 +0100 Received: from aurel32 by volta.aurel32.net with local (Exim 4.77) (envelope-from ) id 1Rljek-0008Pe-Jx; Fri, 13 Jan 2012 17:07:06 +0100 Date: Fri, 13 Jan 2012 17:07:06 +0100 From: Aurelien Jarno To: Dong Xu Wang Message-ID: <20120113160706.GC6244@volta.aurel32.net> References: <1325966978-940-1-git-send-email-aurelien@aurel32.net> <1325966978-940-5-git-send-email-aurelien@aurel32.net> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Mailer: Mutt 1.5.21 (2010-09-15) User-Agent: Mutt/1.5.21 (2010-09-15) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 88.191.126.93 Cc: qemu-devel@nongnu.org, qemu-stable@nongnu.org Subject: Re: [Qemu-devel] [PATCH 4/4] target-i386: fix SSE rounding and flush to zero X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On Thu, Jan 12, 2012 at 01:37:59PM +0800, Dong Xu Wang wrote: > After applied this patch, while I was compiling on my lap, there will > be an error: > > ./configure --enable-kvm --target-list=x86_64-softmmu && make > CC x86_64-softmmu/translate.o > /qemu/target-i386/translate.c: In function ‘disas_insn’: > /qemu/target-i386/translate.c:7547:17: error: incompatible type for > argument 1 of ‘gen_helper_ldmxcsr’ > /qemu/target-i386/helper.h:200:1: note: expected ‘TCGv_i32’ but > argument is of type ‘TCGv_i64’ > make[1]: *** [translate.o] Error 1 > make: *** [subdir-x86_64-softmmu] Error 2 Sorry about that, I have pushed the following patch which solves the problem. target-i386: fix compilation with --enable-debug-tcg Commit 2355c16e74ffa4d14e7fc2b4a23b055565ac0221 introduced a new ldmxcsr helper taking an i32 argument, but the helper is actually passed a long. Fix that by truncating the long to i32. Signed-off-by: Aurelien Jarno --- target-i386/translate.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index b9839c5..860b4a3 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -7544,7 +7544,8 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_lea_modrm(s, modrm, ®_addr, &offset_addr); if (op == 2) { gen_op_ld_T0_A0(OT_LONG + s->mem_index); - gen_helper_ldmxcsr(cpu_T[0]); + tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); + gen_helper_ldmxcsr(cpu_tmp2_i32); } else { tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr)); gen_op_st_T0_A0(OT_LONG + s->mem_index);