From patchwork Sun Sep 18 00:28:16 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Johnson X-Patchwork-Id: 115179 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CB5DA1007D1 for ; Sun, 18 Sep 2011 10:28:53 +1000 (EST) Received: from localhost ([::1]:43463 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R55FX-0008Rs-83 for incoming@patchwork.ozlabs.org; Sat, 17 Sep 2011 20:28:47 -0400 Received: from eggs.gnu.org ([140.186.70.92]:50287) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R55FR-0008Ra-Gw for qemu-devel@nongnu.org; Sat, 17 Sep 2011 20:28:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R55FQ-0007F0-Cr for qemu-devel@nongnu.org; Sat, 17 Sep 2011 20:28:41 -0400 Received: from dns1.mips.com ([12.201.5.69]:44197) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R55FQ-0007Eu-41 for qemu-devel@nongnu.org; Sat, 17 Sep 2011 20:28:40 -0400 Received: from exchdb01.mips.com (exchhub01.mips.com [192.168.36.84]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id p8I0SPif010191; Sat, 17 Sep 2011 17:28:26 -0700 Received: from linux-ericj.mips.com (192.168.65.46) by exchhub01.mips.com (192.168.36.84) with Microsoft SMTP Server id 14.1.270.1; Sat, 17 Sep 2011 17:28:21 -0700 Received: from linux-ericj.mips.com (localhost.localdomain [127.0.0.1]) by linux-ericj.mips.com (8.13.1/8.13.1) with ESMTP id p8I0SLXR010153; Sat, 17 Sep 2011 17:28:21 -0700 Received: (from ericj@localhost) by linux-ericj.mips.com (8.13.1/8.13.1/Submit) id p8I0SGHQ010151; Sat, 17 Sep 2011 17:28:16 -0700 Date: Sat, 17 Sep 2011 17:28:16 -0700 From: Eric Johnson To: , Message-ID: <20110918002816.GA10076@linux-ericj.mips.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.4.1i X-EMS-Proccessed: 6LP3oGfGVdcdb8o1aBnt6w== X-EMS-STAMP: O/3omajToRJaUta83/zHvg== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 12.201.5.69 Subject: [Qemu-devel] [PATCH] Allow microMIPS SWP and SDP to have RD equal to BASE. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The microMIPS SWP and SDP instructions do not modify GPRs. So their behavior is well defined when RD equals BASE. The MIPS Architecture Verification Programs (AVPs) check that they work as expected. This is required for AVPs to pass. Signed-off-by: Eric Johnson --- target-mips/translate.c | 10 +++++++++- 1 files changed, 9 insertions(+), 1 deletions(-) The patch applies to a8467c7a0e8b024a18608ff7db31ca2f2297e641. diff --git a/target-mips/translate.c b/target-mips/translate.c index d5b1c76..82cf75b 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -10034,7 +10034,7 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, const char *opn = "ldst_pair"; TCGv t0, t1; - if (ctx->hflags & MIPS_HFLAG_BMASK || rd == 31 || rd == base) { + if (ctx->hflags & MIPS_HFLAG_BMASK || rd == 31) { generate_exception(ctx, EXCP_RI); return; } @@ -10046,6 +10046,10 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, switch (opc) { case LWP: + if (rd == base) { + generate_exception(ctx, EXCP_RI); + return; + } save_cpu_state(ctx, 0); op_ld_lw(t1, t0, ctx); gen_store_gpr(t1, rd); @@ -10067,6 +10071,10 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, break; #ifdef TARGET_MIPS64 case LDP: + if (rd == base) { + generate_exception(ctx, EXCP_RI); + return; + } save_cpu_state(ctx, 0); op_ld_ld(t1, t0, ctx); gen_store_gpr(t1, rd);