From patchwork Wed May 18 02:38:31 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 96116 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B4DE31007D1 for ; Wed, 18 May 2011 12:38:50 +1000 (EST) Received: from localhost ([::1]:59138 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QMWeq-0005gC-S8 for incoming@patchwork.ozlabs.org; Tue, 17 May 2011 22:38:44 -0400 Received: from eggs.gnu.org ([140.186.70.92]:37017) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QMWej-0005fs-FF for qemu-devel@nongnu.org; Tue, 17 May 2011 22:38:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QMWei-0006QG-Ar for qemu-devel@nongnu.org; Tue, 17 May 2011 22:38:37 -0400 Received: from mail.valinux.co.jp ([210.128.90.3]:46804) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QMWeh-0006Q5-Rr for qemu-devel@nongnu.org; Tue, 17 May 2011 22:38:36 -0400 Received: from ps.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with SMTP id BC1241898E; Wed, 18 May 2011 11:38:31 +0900 (JST) Received: (nullmailer pid 11068 invoked by uid 1000); Wed, 18 May 2011 02:38:31 -0000 Date: Wed, 18 May 2011 11:38:31 +0900 From: Isaku Yamahata To: Jan Kiszka Message-ID: <20110518023831.GD1705@valinux.co.jp> References: <20110516215523.1d77baf4@shadowfax.no-ip.com> <4DD2209B.6080502@siemens.com> <20110517135724.GB1705@valinux.co.jp> <4DD28457.9010604@siemens.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <4DD28457.9010604@siemens.com> User-Agent: Mutt/1.5.19 (2009-01-05) X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 210.128.90.3 Cc: "adnan@khaleel.us" , "qemu-devel@nongnu.org" Subject: Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci express support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On Tue, May 17, 2011 at 04:21:11PM +0200, Jan Kiszka wrote: > I also succeeded with passing through a PCIe host device. Nicely, the > full set capabilities showed up on the guest side this way. But GPU > pass-through did not improve this way (it rather regressed, yet unclear > why). Interesting. > > I had a quick look at your patches. > > With seabios patch of 94710189f5323034e00b510fe5a0865a7b576a9f, > > you ignored MCFG area. > > > > (start = Q35_HOST_BRIDGE_PCIEXBAR_ADDR, size = 256MB) is used > > for MCFG (!= pci region), so it can't be used for PCI region. > > That's why 256M is added to s. > > And Q35_HOST_BRIDGE_PCIEXBAR_ADDR in dev-q35.h also needs to be adjusted. > > Confused. Where was the PCI region located without my hack? I mean the following patch on top of your tree. At the moment, I only compiled it. > BTW, the PCI bar mapping failures of VGA or e1000 are independent of > that seabios commit. You should see them with your tree as well. Hmm, I'll look into it. > > After pushing out pci id clean up and once they are accepted, > > I'll publish rebased/cleaned up one. > > Note that I dropped "simply i440fx initialization". It was a premature > cleanup that caused regressions. The good news: I'm working on PAM/SMRAM > fixes that will include such a cleanup after removing the need for the > init function. The bad news: Those patches will force you to rebase > again (to break out the new PAM/SMRAM code). Please keep CCed on me. diff --git a/src/dev-q35.c b/src/dev-q35.c index c0aa057..eee50c4 100644 --- a/src/dev-q35.c +++ b/src/dev-q35.c @@ -36,13 +36,15 @@ void mch_mem_addr_init(u16 bdf, void *arg) /* * BUILD_MAX_HIGHMEM == 0xc0000000 - * [0xc000 0000, 0xf000 0000) for MCFG - * 4GB - 1GB, 4GB - 256MB + * [0xc000 0000, 0xd000 0000) for MCFG + * 3GB , 3GB + 256MB + * [0xd000 0000, 0xf000 0000) for pci memory region + * 3GB + 256MB, 4GB - 256MB * [0xf000 0000, 0xfec0 0000) for DMI interface(subtractive decode) * 4GB - 256MB, 4GB - 20MB */ - s = BUILD_MAX_HIGHMEM; - e = s + 128 * 1024 * 1024 - 1 + 512 * 1024 * 1024; + s = Q35_HOST_BRIDGE_PCIEXBAR_ADDR + Q35_HOST_BRIDGE_PCIEXBAR_SIZE; + e = s + 512 * 1024 * 1024 - 1; pci_region_init(addr->pci_bios_mem_region, s, e); /* pci_bios_mem_addr + */ diff --git a/src/dev-q35.h b/src/dev-q35.h index f5cae62..0d83dba 100644 --- a/src/dev-q35.h +++ b/src/dev-q35.h @@ -8,7 +8,7 @@ #define Q35_HOST_BRIDGE_SMRAM 0x9d #define Q35_HOST_BRIDGE_PCIEXBAR 0x60 #define Q35_HOST_BRIDGE_PCIEXBAR_SIZE (256 * 1024 * 1024) -#define Q35_HOST_BRIDGE_PCIEXBAR_ADDR 0xe0000000 +#define Q35_HOST_BRIDGE_PCIEXBAR_ADDR BUILD_MAX_HIGHMEM #define Q35_HOST_BRIDGE_PCIEXBAREN ((u64)1) #define Q35_HOST_PCIE_PCI_SEGMENT 0 #define Q35_HOST_PCIE_START_BUS_NUMBER 0