From patchwork Fri Nov 19 12:08:19 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael S. Tsirkin" X-Patchwork-Id: 72243 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 321FD1007D2 for ; Fri, 19 Nov 2010 23:10:00 +1100 (EST) Received: from localhost ([127.0.0.1]:40328 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PJPmn-0006P0-Hp for incoming@patchwork.ozlabs.org; Fri, 19 Nov 2010 07:09:49 -0500 Received: from [140.186.70.92] (port=54909 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PJPlf-00063a-8Y for qemu-devel@nongnu.org; Fri, 19 Nov 2010 07:08:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PJPlX-00043B-Il for qemu-devel@nongnu.org; Fri, 19 Nov 2010 07:08:39 -0500 Received: from mx1.redhat.com ([209.132.183.28]:32563) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PJPlX-00042z-Aj for qemu-devel@nongnu.org; Fri, 19 Nov 2010 07:08:31 -0500 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id oAJC8TtH027226 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Fri, 19 Nov 2010 07:08:29 -0500 Received: from redhat.com (vpn-6-195.tlv.redhat.com [10.35.6.195]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with SMTP id oAJC8QPq023220; Fri, 19 Nov 2010 07:08:27 -0500 Date: Fri, 19 Nov 2010 14:08:19 +0200 From: "Michael S. Tsirkin" To: Isaku Yamahata Message-ID: <20101119120819.GA5867@redhat.com> References: <48f736e1a86a0db8ad368a42103d4e366a2dbd22.1289969012.git.yamahata@valinux.co.jp> <20101118070530.GB15274@redhat.com> <20101118072910.GR18102@valinux.co.jp> <20101118084625.GA16832@redhat.com> <20101119081519.GA16942@valinux.co.jp> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20101119081519.GA16942@valinux.co.jp> User-Agent: Mutt/1.5.21 (2010-09-15) X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. Cc: skandasa@cisco.com, Anthony Liguori , etmartin@cisco.com, qemu-devel@nongnu.org, wexu2@cisco.com Subject: [Qemu-devel] Re: [PATCH 7/7] pci bridge: implement secondary bus reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On Fri, Nov 19, 2010 at 05:15:19PM +0900, Isaku Yamahata wrote: > On Thu, Nov 18, 2010 at 10:46:25AM +0200, Michael S. Tsirkin wrote: > > On Thu, Nov 18, 2010 at 04:29:10PM +0900, Isaku Yamahata wrote: > > > On Thu, Nov 18, 2010 at 09:05:30AM +0200, Michael S. Tsirkin wrote: > > > > On Wed, Nov 17, 2010 at 01:50:27PM +0900, Isaku Yamahata wrote: > > > > > Emulates secondary bus reset when secondary bus reset bit > > > > > is written from 0 to 1. > > > > > > > > > > Signed-off-by: Isaku Yamahata > > > > > Signed-off-by: Anthony Liguori > > > > > --- > > > > > hw/pci_bridge.c | 12 +++++++++++- > > > > > 1 files changed, 11 insertions(+), 1 deletions(-) > > > > > > > > > > diff --git a/hw/pci_bridge.c b/hw/pci_bridge.c > > > > > index 58cc2e4..618a81e 100644 > > > > > --- a/hw/pci_bridge.c > > > > > +++ b/hw/pci_bridge.c > > > > > @@ -139,6 +139,10 @@ pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type) > > > > > void pci_bridge_write_config(PCIDevice *d, > > > > > uint32_t address, uint32_t val, int len) > > > > > { > > > > > + PCIBridge *s = container_of(d, PCIBridge, dev); > > > > > + uint16_t bridge_control = pci_get_word(d->config + PCI_BRIDGE_CONTROL); > > > > > + uint16_t bridge_control_new; > > > > > + > > > > > pci_default_write_config(d, address, val, len); > > > > > > > > > > if (/* io base/limit */ > > > > > @@ -147,9 +151,15 @@ void pci_bridge_write_config(PCIDevice *d, > > > > > /* memory base/limit, prefetchable base/limit and > > > > > io base/limit upper 16 */ > > > > > ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) { > > > > > - PCIBridge *s = container_of(d, PCIBridge, dev); > > > > > pci_bridge_update_mappings(&s->sec_bus); > > > > > } > > > > > + > > > > > + bridge_control_new = pci_get_word(d->config + PCI_BRIDGE_CONTROL); > > > > > + if (!(bridge_control & PCI_BRIDGE_CTL_BUS_RESET) && > > > > > + (bridge_control_new & PCI_BRIDGE_CTL_BUS_RESET)) { > > > > > + /* 0 -> 1 */ > > > > > + pci_bus_reset(&s->sec_bus); > > > > > + } > > > > > } > > > > > > > > > > void pci_bridge_disable_base_limit(PCIDevice *dev) > > > > > > > > Presumably this bit will have to be made writeable? > > > > > > Yes, it's already writable. > > > static void pci_init_wmask_bridge(PCIDevice *d) > > > ... > > > pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff); > > > > Ouch, that's wrong, isn't it? > > Bits 15:12 are reserved, readonly, 0. > > > > I think we need the following (untested). > > Comments? > > Basically it looks good if you left bits 8-11 RO intentional. > qemu doesn't emulate pci bus cycles, so it won't matter. > So this on top? diff --git a/hw/pci.c b/hw/pci.c index 7d6d5ad..75da4f7 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -589,7 +589,11 @@ static void pci_init_wmask_bridge(PCIDevice *d) memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); /* TODO: add this define to pci_regs.h in linux and then in qemu. */ -#define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */ +#define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */ +#define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */ +#define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */ +#define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */ +#define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */ pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR | @@ -598,7 +602,15 @@ static void pci_init_wmask_bridge(PCIDevice *d) PCI_BRIDGE_CTL_VGA_16BIT | PCI_BRIDGE_CTL_MASTER_ABORT | PCI_BRIDGE_CTL_BUS_RESET | - PCI_BRIDGE_CTL_FAST_BACK); + PCI_BRIDGE_CTL_FAST_BACK | + PCI_BRIDGE_CTL_DISCARD | + PCI_BRIDGE_CTL_SEC_DISCARD | + PCI_BRIDGE_CTL_DISCARD_STATUS | + PCI_BRIDGE_CTL_DISCARD_SERR); + /* Below does not do anything as we never set this bit, put here for + * completeness. */ + pci_set_word(d->w1mask + PCI_BRIDGE_CONTROL, + PCI_BRIDGE_CTL_DISCARD_STATUS); } static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)