From patchwork Tue Nov 16 13:14:53 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael S. Tsirkin" X-Patchwork-Id: 71395 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 36251B711C for ; Wed, 17 Nov 2010 00:16:12 +1100 (EST) Received: from localhost ([127.0.0.1]:34217 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PILOL-0006Ag-B0 for incoming@patchwork.ozlabs.org; Tue, 16 Nov 2010 08:16:09 -0500 Received: from [140.186.70.92] (port=35308 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PILNH-0005mQ-Q8 for qemu-devel@nongnu.org; Tue, 16 Nov 2010 08:15:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PILNG-0001Da-J4 for qemu-devel@nongnu.org; Tue, 16 Nov 2010 08:15:03 -0500 Received: from mx1.redhat.com ([209.132.183.28]:18079) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PILNG-0001DU-9y for qemu-devel@nongnu.org; Tue, 16 Nov 2010 08:15:02 -0500 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id oAGDF1UF032137 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Tue, 16 Nov 2010 08:15:01 -0500 Received: from redhat.com (dhcp-1-105.tlv.redhat.com [10.35.1.105]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with SMTP id oAGDExho012695; Tue, 16 Nov 2010 08:15:00 -0500 Date: Tue, 16 Nov 2010 15:14:53 +0200 From: mst@redhat.com To: qemu-devel@nongnu.org Message-ID: <20101116131452.GA23963@redhat.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. Cc: Bernhard Kohl Subject: [Qemu-devel] [PATCH comment tweaked] msix: allow byte and word reading from mmio X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Although explicitly disallowed by the PCI spec, some guests read a single byte or word from mmio. Likely a guest OS bug, but I have an OS which reads single bytes and it works fine on real hardware. Signed-off-by: Bernhard Kohl Signed-off-by: Michael S. Tsirkin --- OK so it could like something like the below. However, my question is: do we need to put this in or can the guest simply be fixed? hw/msix.c | 31 +++++++++++++++++++++++++++---- 1 files changed, 27 insertions(+), 4 deletions(-) diff --git a/hw/msix.c b/hw/msix.c index f66d255..38dff59 100644 --- a/hw/msix.c +++ b/hw/msix.c @@ -102,10 +102,28 @@ static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr) return pci_get_long(page + offset); } -static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr) + /* Note: + * PCI spec requires that all MSI-X table accesses are either DWORD or QWORD, + * size aligned. Some guests seem to violate this rule for read accesses, + * performing single byte reads. Since it's easy to support this, let's do so. + * Also support 16 bit size aligned reads, just in case. + */ +static uint32_t msix_mmio_readw(void *opaque, target_phys_addr_t addr) { - fprintf(stderr, "MSI-X: only dword read is allowed!\n"); - return 0; + PCIDevice *dev = opaque; + unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x1; + void *page = dev->msix_table_page; + + return pci_get_word(page + offset); +} + +static uint32_t msix_mmio_readb(void *opaque, target_phys_addr_t addr) +{ + PCIDevice *dev = opaque; + unsigned int offset = addr & (MSIX_PAGE_SIZE - 1); + void *page = dev->msix_table_page; + + return pci_get_byte(page + offset); } static uint8_t msix_pending_mask(int vector) @@ -192,6 +210,11 @@ static void msix_mmio_writel(void *opaque, target_phys_addr_t addr, msix_handle_mask_update(dev, vector); } +/* PCI spec: + * For all accesses to MSI-X Table and MSI-X PBA fields, software must use + * aligned full DWORD or aligned full QWORD transactions; otherwise, the result + * is undefined. + */ static void msix_mmio_write_unallowed(void *opaque, target_phys_addr_t addr, uint32_t val) { @@ -203,7 +226,7 @@ static CPUWriteMemoryFunc * const msix_mmio_write[] = { }; static CPUReadMemoryFunc * const msix_mmio_read[] = { - msix_mmio_read_unallowed, msix_mmio_read_unallowed, msix_mmio_readl + msix_mmio_readb, msix_mmio_readw, msix_mmio_readl }; /* Should be called from device's map method. */