From patchwork Fri Nov 12 02:56:27 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Williamson X-Patchwork-Id: 70920 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 97F20B7139 for ; Fri, 12 Nov 2010 14:08:57 +1100 (EST) Received: from localhost ([127.0.0.1]:48302 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PGjte-0003Dq-FL for incoming@patchwork.ozlabs.org; Thu, 11 Nov 2010 22:01:50 -0500 Received: from [140.186.70.92] (port=48585 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PGjqE-00030Q-T4 for qemu-devel@nongnu.org; Thu, 11 Nov 2010 21:58:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PGjoU-0000XO-7v for qemu-devel@nongnu.org; Thu, 11 Nov 2010 21:56:31 -0500 Received: from mx1.redhat.com ([209.132.183.28]:37084) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PGjoT-0000X7-Ty for qemu-devel@nongnu.org; Thu, 11 Nov 2010 21:56:30 -0500 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id oAC2uTR2028816 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Thu, 11 Nov 2010 21:56:29 -0500 Received: from s20.home (ovpn01.gateway.prod.ext.phx2.redhat.com [10.5.9.1]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id oAC2uRj5011818; Thu, 11 Nov 2010 21:56:28 -0500 From: Alex Williamson To: kvm@vger.kernel.org Date: Thu, 11 Nov 2010 19:56:27 -0700 Message-ID: <20101112025620.31423.18281.stgit@s20.home> In-Reply-To: <20101112024710.31423.99667.stgit@s20.home> References: <20101112024710.31423.99667.stgit@s20.home> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. Cc: chrisw@redhat.com, alex.williamson@redhat.com, qemu-devel@nongnu.org, mst@redhat.com Subject: [Qemu-devel] [PATCH 7/8] pci: Pass ID for capability read/write handlers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Any handlers that actually want to interact with specific capabilities are going to want to know the capability ID being accessed. With the capability map, this is readily available, so we can save handlers the trouble of figuring it out. Signed-off-by: Alex Williamson --- hw/device-assignment.c | 36 ++++++++++++++++++++++-------------- hw/pci.c | 14 ++++++++------ hw/pci.h | 8 ++++---- 3 files changed, 34 insertions(+), 24 deletions(-) diff --git a/hw/device-assignment.c b/hw/device-assignment.c index 39f19be..179c7dc 100644 --- a/hw/device-assignment.c +++ b/hw/device-assignment.c @@ -1244,30 +1244,38 @@ static void assigned_dev_update_msix(PCIDevice *pci_dev, unsigned int ctrl_pos) #endif #endif -static void assigned_device_pci_cap_write_config(PCIDevice *pci_dev, uint32_t address, +static void assigned_device_pci_cap_write_config(PCIDevice *pci_dev, + uint8_t cap_id, + uint32_t address, uint32_t val, int len) { - AssignedDevice *assigned_dev = container_of(pci_dev, AssignedDevice, dev); + pci_default_cap_write_config(pci_dev, cap_id, address, val, len); - pci_default_cap_write_config(pci_dev, address, val, len); + switch (cap_id) { #ifdef KVM_CAP_IRQ_ROUTING + case PCI_CAP_ID_MSI: #ifdef KVM_CAP_DEVICE_MSI - if (assigned_dev->cap.available & ASSIGNED_DEVICE_CAP_MSI) { - int pos = pci_find_capability(pci_dev, PCI_CAP_ID_MSI); - if (ranges_overlap(address, len, pos + PCI_MSI_FLAGS, 1)) { - assigned_dev_update_msi(pci_dev, pos + PCI_MSI_FLAGS); + { + uint8_t cap = pci_find_capability(pci_dev, cap_id); + if (ranges_overlap(address - cap, len, PCI_MSI_FLAGS, 1)) { + assigned_dev_update_msi(pci_dev, cap + PCI_MSI_FLAGS); + } } - } #endif + break; + + case PCI_CAP_ID_MSIX: #ifdef KVM_CAP_DEVICE_MSIX - if (assigned_dev->cap.available & ASSIGNED_DEVICE_CAP_MSIX) { - int pos = pci_find_capability(pci_dev, PCI_CAP_ID_MSIX); - if (ranges_overlap(address, len, pos + PCI_MSIX_FLAGS + 1, 1)) { - assigned_dev_update_msix(pci_dev, pos + PCI_MSIX_FLAGS); - } - } + { + uint8_t cap = pci_find_capability(pci_dev, cap_id); + if (ranges_overlap(address - cap, len, PCI_MSIX_FLAGS + 1, 1)) { + assigned_dev_update_msix(pci_dev, cap + PCI_MSIX_FLAGS); + } + } #endif + break; #endif + } return; } diff --git a/hw/pci.c b/hw/pci.c index d566e33..e1c0917 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -1168,10 +1168,11 @@ static uint32_t pci_read_config(PCIDevice *d, uint32_t pci_default_read_config(PCIDevice *d, uint32_t address, int len) { + uint8_t cap_id; assert(len == 1 || len == 2 || len == 4); - if (pci_access_cap_config(d, address, len)) { - return d->cap.config_read(d, address, len); + if ((cap_id = pci_access_cap_config(d, address, len))) { + return d->cap.config_read(d, cap_id, address, len); } return pci_read_config(d, address, len); @@ -1193,13 +1194,13 @@ int pci_access_cap_config(PCIDevice *pci_dev, uint32_t address, int len) return pci_dev->cap_map[address]; } -uint32_t pci_default_cap_read_config(PCIDevice *pci_dev, +uint32_t pci_default_cap_read_config(PCIDevice *pci_dev, uint8_t cap_id, uint32_t address, int len) { return pci_read_config(pci_dev, address, len); } -void pci_default_cap_write_config(PCIDevice *pci_dev, +void pci_default_cap_write_config(PCIDevice *pci_dev, uint8_t cap_id, uint32_t address, uint32_t val, int len) { pci_write_config(pci_dev, address, val, len); @@ -1208,9 +1209,10 @@ void pci_default_cap_write_config(PCIDevice *pci_dev, void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) { int was_irq_disabled = pci_irq_disabled(d); + uint8_t cap_id; - if (pci_access_cap_config(d, addr, l)) { - d->cap.config_write(d, addr, val, l); + if ((cap_id = pci_access_cap_config(d, addr, l))) { + d->cap.config_write(d, cap_id, addr, val, l); return; } diff --git a/hw/pci.h b/hw/pci.h index 177008a..3f0b4e0 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -83,9 +83,9 @@ typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, pcibus_t addr, pcibus_t size, int type); typedef int PCIUnregisterFunc(PCIDevice *pci_dev); -typedef void PCICapConfigWriteFunc(PCIDevice *pci_dev, +typedef void PCICapConfigWriteFunc(PCIDevice *pci_dev, uint8_t cap_id, uint32_t address, uint32_t val, int len); -typedef uint32_t PCICapConfigReadFunc(PCIDevice *pci_dev, +typedef uint32_t PCICapConfigReadFunc(PCIDevice *pci_dev, uint8_t cap_id, uint32_t address, int len); typedef struct PCIIORegion { @@ -245,9 +245,9 @@ void pci_default_write_config(PCIDevice *d, uint32_t address, uint32_t val, int len); void pci_device_save(PCIDevice *s, QEMUFile *f); int pci_device_load(PCIDevice *s, QEMUFile *f); -uint32_t pci_default_cap_read_config(PCIDevice *pci_dev, +uint32_t pci_default_cap_read_config(PCIDevice *pci_dev, uint8_t cap_id, uint32_t address, int len); -void pci_default_cap_write_config(PCIDevice *pci_dev, +void pci_default_cap_write_config(PCIDevice *pci_dev, uint8_t cap_id, uint32_t address, uint32_t val, int len); int pci_access_cap_config(PCIDevice *pci_dev, uint32_t address, int len);