From patchwork Tue Feb 9 20:12:34 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 44964 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 6BA27B7DBE for ; Wed, 10 Feb 2010 08:58:58 +1100 (EST) Received: from localhost ([127.0.0.1]:53058 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Nexyf-0005Cq-Ut for incoming@patchwork.ozlabs.org; Tue, 09 Feb 2010 16:50:38 -0500 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Nexqi-0002dr-Qg for qemu-devel@nongnu.org; Tue, 09 Feb 2010 16:42:24 -0500 Received: from [199.232.76.173] (port=49445 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Nexqg-0002cO-Sl for qemu-devel@nongnu.org; Tue, 09 Feb 2010 16:42:23 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1Nexqa-0003oj-NY for qemu-devel@nongnu.org; Tue, 09 Feb 2010 16:42:22 -0500 Received: from are.twiddle.net ([75.149.56.221]:60029) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NexqZ-0003oG-NK for qemu-devel@nongnu.org; Tue, 09 Feb 2010 16:42:15 -0500 Received: by are.twiddle.net (Postfix, from userid 5000) id 7E711C29; Tue, 9 Feb 2010 13:42:14 -0800 (PST) From: Richard Henderson Date: Tue, 9 Feb 2010 12:12:34 -0800 To: qemu-devel@nongnu.org Message-Id: <20100209214214.7E711C29@are.twiddle.net> X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH] tcg-mips: Implement setcond2. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c | 29 +++++++++++++++++++++++++++++ 1 files changed, 29 insertions(+), 0 deletions(-) diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index d181ff1..3a53221 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -643,6 +643,30 @@ static void tcg_out_setcond(TCGContext *s, int cond, int ret, } } +static void tcg_out_setcond2(TCGContext *s, int cond, int ret, + int al, int ah, int bl, int bh) +{ + switch (cond) { + case TCG_COND_EQ: + tcg_out_setcond(s, TCG_COND_EQ, TCG_REG_T0, al, bl); + tcg_out_setcond(s, TCG_COND_EQ, ret, ah, bh); + tcg_out_opc_reg(s, OPC_AND, ret, ret, TCG_REG_T0); + break; + case TCG_COND_NE: + tcg_out_setcond(s, TCG_COND_NE, TCG_REG_T0, al, bl); + tcg_out_setcond(s, TCG_COND_NE, ret, ah, bh); + tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_REG_T0); + break; + default: + tcg_out_setcond(s, tcg_unsigned_cond(cond), TCG_REG_T0, al, bl); + tcg_out_setcond(s, TCG_COND_EQ, TCG_REG_AT, ah, bh); + tcg_out_opc_reg(s, OPC_AND, TCG_REG_T0, TCG_REG_T0, TCG_REG_AT); + tcg_out_setcond(s, cond, ret, ah, bh); + tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_REG_T0); + break; + } +} + #if defined(CONFIG_SOFTMMU) #include "../../softmmu_defs.h" @@ -1218,6 +1242,10 @@ static inline void tcg_out_op(TCGContext *s, int opc, case INDEX_op_setcond_i32: tcg_out_setcond(s, args[3], args[0], args[1], args[2]); break; + case INDEX_op_setcond2_i32: + tcg_out_setcond2(s, args[5], args[0], args[1], args[2], + args[3], args[4]); + break; case INDEX_op_qemu_ld8u: tcg_out_qemu_ld(s, args, 0); @@ -1297,6 +1325,7 @@ static const TCGTargetOpDef mips_op_defs[] = { { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rJZ", "rJZ" } }, { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJZ", "rJZ" } }, { INDEX_op_brcond2_i32, { "rZ", "rZ", "rZ", "rZ" } }, + { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } }, #if TARGET_LONG_BITS == 32 { INDEX_op_qemu_ld8u, { "L", "lZ" } },