From patchwork Wed Nov 25 16:59:06 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael S. Tsirkin" X-Patchwork-Id: 39350 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1610AB7BC6 for ; Thu, 26 Nov 2009 04:13:13 +1100 (EST) Received: from localhost ([127.0.0.1]:52280 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NDLQT-0002E6-Qh for incoming@patchwork.ozlabs.org; Wed, 25 Nov 2009 12:13:09 -0500 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NDLFU-0004Eu-U0 for qemu-devel@nongnu.org; Wed, 25 Nov 2009 12:01:49 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NDLFS-0004DO-Kk for qemu-devel@nongnu.org; Wed, 25 Nov 2009 12:01:47 -0500 Received: from [199.232.76.173] (port=42654 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NDLFR-0004D3-MQ for qemu-devel@nongnu.org; Wed, 25 Nov 2009 12:01:45 -0500 Received: from mx1.redhat.com ([209.132.183.28]:6958) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NDLFQ-0003vu-Sq for qemu-devel@nongnu.org; Wed, 25 Nov 2009 12:01:45 -0500 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id nAPH1hHB002653 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Wed, 25 Nov 2009 12:01:43 -0500 Received: from redhat.com (vpn1-4-179.ams2.redhat.com [10.36.4.179]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with SMTP id nAPH1fj9032713; Wed, 25 Nov 2009 12:01:42 -0500 Date: Wed, 25 Nov 2009 18:59:06 +0200 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org, anthony@codemonkey.ws, yamahata@valinux.co.jp Message-ID: <20091125165906.GE24783@redhat.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.19 (2009-01-05) X-Scanned-By: MIMEDefang 2.67 on 10.5.11.11 X-detected-operating-system: by monty-python.gnu.org: Genre and OS details not recognized. Cc: Subject: [Qemu-devel] [PATCH 4/4] pci: interrupt disable bit support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org interrupt disable bit is mandatory in PCI spec, so we must implement it to be spec compliant. Signed-off-by: Michael S. Tsirkin --- hw/pci.c | 57 ++++++++++++++++++++++++++++++++++++++++----------------- hw/pci.h | 4 ++++ 2 files changed, 44 insertions(+), 17 deletions(-) diff --git a/hw/pci.c b/hw/pci.c index 844664b..3daae46 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -114,12 +114,43 @@ static void pci_update_irq_status(PCIDevice *dev) } } +static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) +{ + PCIBus *bus; + for (;;) { + bus = pci_dev->bus; + irq_num = bus->map_irq(pci_dev, irq_num); + if (bus->set_irq) + break; + pci_dev = bus->parent_dev; + } + bus->irq_count[irq_num] += change; + bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); +} + +/* Update irq disabled field after config space change, + * assert/deassert interrupts if necessary. */ +static void pci_update_irq_disabled(PCIDevice *d) +{ + int i; + int disabled = !!(pci_get_word(d->config + PCI_COMMAND) & + PCI_COMMAND_INTX_DISABLE); + if (disabled == d->irq_disabled) + return; + d->irq_disabled = disabled; + for (i = 0; i < ARRAY_SIZE(d->irq_state); ++i) { + int state = d->irq_state[i]; + pci_change_irq_level(d, i, disabled ? -state : state); + } +} + static void pci_device_reset(PCIDevice *dev) { int r; memset(dev->irq_state, 0, sizeof dev->irq_state); dev->irq_status = 0; + dev->irq_disabled = 0; pci_update_irq_status(dev); dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); @@ -345,6 +376,7 @@ int pci_device_load(PCIDevice *s, QEMUFile *f) } /* Restore the interrupt status bit. */ pci_update_irq_status(s); + pci_update_irq_disabled(s); return ret; } @@ -458,7 +490,8 @@ static void pci_init_wmask(PCIDevice *dev) dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; dev->wmask[PCI_INTERRUPT_LINE] = 0xff; pci_set_word(dev->wmask + PCI_COMMAND, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | + PCI_COMMAND_INTX_DISABLE); memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, config_size - PCI_CONFIG_HEADER_SIZE); @@ -903,26 +936,14 @@ void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || range_covers_byte(addr, l, PCI_COMMAND)) pci_update_mappings(d); + + if (range_covers_byte(addr, l, PCI_COMMAND)) + pci_update_irq_disabled(d); } /***********************************************************/ /* generic PCI irq support */ -static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) -{ - PCIBus *bus; - for (;;) { - bus = pci_dev->bus; - irq_num = bus->map_irq(pci_dev, irq_num); - if (bus->set_irq) - break; - pci_dev = bus->parent_dev; - } - bus->irq_count[irq_num] += change; - bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); -} - - /* 0 <= irq_num <= 3. level must be 0 or 1 */ static void pci_set_irq(void *opaque, int irq_num, int level) { @@ -935,7 +956,9 @@ static void pci_set_irq(void *opaque, int irq_num, int level) pci_dev->irq_state[irq_num] = level; pci_dev->irq_status += change; - pci_update_irq_status(s); + pci_update_irq_status(pci_dev); + if (pci_dev->irq_disabled) + return; pci_change_irq_level(pci_dev, irq_num, change); } diff --git a/hw/pci.h b/hw/pci.h index c3f2c3f..994b8bc 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -101,6 +101,7 @@ typedef struct PCIIORegion { #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ #define PCI_COMMAND_MASTER 0x4 /* Enable bus master */ +#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ #define PCI_STATUS 0x06 /* 16 bits */ #define PCI_STATUS_INTERRUPT 0x08 #define PCI_REVISION_ID 0x08 /* 8 bits */ @@ -226,6 +227,9 @@ struct PCIDevice { /* Sum of all irq levels. Used to implement irq status register. */ int irq_status; + /* Whether interrupts are disabled by command bit. */ + int irq_disabled; + /* Capability bits */ uint32_t cap_present;