| Message ID | 20091125113903.GC9322@redhat.com |
|---|---|
| State | New |
| Headers | show |
diff --git a/hw/msix.c b/hw/msix.c index 45f83dd..785e097 100644 --- a/hw/msix.c +++ b/hw/msix.c @@ -361,7 +361,8 @@ void msix_reset(PCIDevice *dev) if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) return; msix_free_irq_entries(dev); - dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] &= MSIX_ENABLE_MASK; + dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] &= + ~dev->wmask[dev->msix_cap + MSIX_ENABLE_OFFSET]; memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE); msix_mask_all(dev, dev->msix_entries_nr); }
On reset, we currently clear all bits in msix control register *except* enable bit. This is wrong: the spec says we should clear writeable bits: function mask and enable bit. Correct this. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> --- hw/msix.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-)