@@ -69,6 +69,8 @@
static uint64_t irq_count[16];
#endif
+static int irq_from_slave;
+
/* set irq level. If an edge is detected, then the IRR is set to 1 */
static inline void pic_set_irq1(PicState *s, int irq, int level)
{
@@ -124,7 +126,7 @@
if (s->special_mask)
mask &= ~s->imr;
if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
- mask &= ~(1 << 2);
+ mask &= ~(1 << irq_from_slave);
cur_priority = get_priority(s, mask);
if (priority < cur_priority) {
/* higher priority found: an irq should be generated */
@@ -145,8 +147,8 @@
irq2 = pic_get_irq(&s->pics[1]);
if (irq2 >= 0) {
/* if irq request by slave pic, signal master PIC */
- pic_set_irq1(&s->pics[0], 2, 1);
- pic_set_irq1(&s->pics[0], 2, 0);
+ pic_set_irq1(&s->pics[0], irq_from_slave, 1);
+ pic_set_irq1(&s->pics[0], irq_from_slave, 0);
}
/* look at requested irq */
irq = pic_get_irq(&s->pics[0]);
@@ -171,6 +173,11 @@
else {
qemu_irq_lower(s->parent_irq);
}
+#elif defined(TARGET_I386)
+ else if (irq_from_slave == 7) {
+ /* NEC PC-98x1 */
+ qemu_irq_lower(s->parent_irq);
+ }
#endif
}
@@ -224,7 +231,7 @@
irq = pic_get_irq(&s->pics[0]);
if (irq >= 0) {
pic_intack(&s->pics[0], irq);
- if (irq == 2) {
+ if (irq == irq_from_slave) {
irq2 = pic_get_irq(&s->pics[1]);
if (irq2 >= 0) {
pic_intack(&s->pics[1], irq2);
@@ -376,12 +383,12 @@
ret = pic_get_irq(s);
if (ret >= 0) {
if (addr1 >> 7) {
- s->pics_state->pics[0].isr &= ~(1 << 2);
- s->pics_state->pics[0].irr &= ~(1 << 2);
+ s->pics_state->pics[0].isr &= ~(1 << irq_from_slave);
+ s->pics_state->pics[0].irr &= ~(1 << irq_from_slave);
}
s->irr &= ~(1 << ret);
s->isr &= ~(1 << ret);
- if (addr1 >> 7 || ret != 2)
+ if (addr1 >> 7 || ret != irq_from_slave)
pic_update_irq(s->pics_state);
} else {
ret = 0x07;
@@ -425,7 +432,7 @@
int ret;
ret = pic_poll_read(&s->pics[0], 0x00);
- if (ret == 2)
+ if (ret == irq_from_slave)
ret = pic_poll_read(&s->pics[1], 0x80) + 8;
/* Prepare for ISR read */
s->pics[0].read_reg_select = 1;
@@ -545,11 +552,54 @@
{
PicState2 *s;
+ irq_from_slave = 2;
+
s = qemu_mallocz(sizeof(PicState2));
pic_init1(0x20, 0x4d0, &s->pics[0]);
pic_init1(0xa0, 0x4d1, &s->pics[1]);
s->pics[0].elcr_mask = 0xf8;
s->pics[1].elcr_mask = 0xde;
+ s->parent_irq = parent_irq;
+ s->pics[0].pics_state = s;
+ s->pics[1].pics_state = s;
+ isa_pic = s;
+ return qemu_allocate_irqs(i8259_set_irq, s, 16);
+}
+
+/* NEC PC-98x1 */
+
+static void pc98_pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ pic_ioport_write(opaque, addr >> 1, val);
+}
+
+static uint32_t pc98_pic_ioport_read(void *opaque, uint32_t addr)
+{
+ return pic_ioport_read(opaque, addr >> 1);
+}
+
+static void pc98_pic_init1(int io_addr, PicState *s)
+{
+ int i;
+ for (i = 0; i < 2; i++) {
+ register_ioport_write(io_addr + (i << 1), 1, 1, pc98_pic_ioport_write, s);
+ register_ioport_read(io_addr + (i << 1), 1, 1, pc98_pic_ioport_read, s);
+ }
+ register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
+ qemu_register_reset(pic_reset, s);
+}
+
+qemu_irq *pc98_i8259_init(qemu_irq parent_irq)
+{
+ PicState2 *s;
+
+ irq_from_slave = 7;
+
+ s = qemu_mallocz(sizeof(PicState2));
+ pc98_pic_init1(0x00, &s->pics[0]);
+ pc98_pic_init1(0x08, &s->pics[1]);
+ s->pics[0].elcr_mask = 0;
+ s->pics[1].elcr_mask = 0;
s->parent_irq = parent_irq;
s->pics[0].pics_state = s;
s->pics[1].pics_state = s;