diff mbox series

[qemu,v3,06/20] Fixing the basic functionality of STM32 timers

Message ID 170152443229.18048.53824064267512246-6@git.sr.ht
State New
Headers show
Series Fix malfunctioning of T2-T5 timers on the STM32 platform | expand

Commit Message

~lbryndza Dec. 2, 2023, 12:13 p.m. UTC 
From: Lucjan Bryndza <lbryndza.oss@icloud.com>

The current implementation of timers does not work properly
even in basic functionality. A counter configured to report
an interrupt every 10ms reports the first interrupts after a
few seconds.  There are also no properly implemented count up an
count down modes. This commit fixes bugs with interrupt
reporting and implements the basic modes of the counter's
time-base block.

Add timer update UIF

Signed-off-by: Lucjan Bryndza <lbryndza.oss@icloud.com>
---
 hw/timer/stm32f2xx_timer.c | 6 ++++++
 1 file changed, 6 insertions(+)
diff mbox series

Patch

diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c
index 62c98b5f04..bd3d1bcf24 100644
--- a/hw/timer/stm32f2xx_timer.c
+++ b/hw/timer/stm32f2xx_timer.c
@@ -90,6 +90,12 @@  static void stm32f2xx_timer_update(STM32F2XXTimerState *s)
     }
 }
 
+static void stm32f2xx_timer_update_uif(STM32F2XXTimerState *s, uint8_t value)
+{
+    s->tim_sr &= ~TIM_SR1_UIF;
+    s->tim_sr |= (value & TIM_SR1_UIF);
+    qemu_set_irq(s->irq, value);
+}
 
 static void stm32f2xx_timer_reset(DeviceState *dev)
 {