From patchwork Sat Dec 2 12:12:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ~lbryndza X-Patchwork-Id: 1870922 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SjB3Q54NJz1ySY for ; Sun, 3 Dec 2023 00:43:46 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r9QEm-00058B-86; Sat, 02 Dec 2023 08:40:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r9QEh-00057F-CA for qemu-devel@nongnu.org; Sat, 02 Dec 2023 08:40:47 -0500 Received: from mail-b.sr.ht ([173.195.146.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r9QEd-0008WO-HK for qemu-devel@nongnu.org; Sat, 02 Dec 2023 08:40:45 -0500 Authentication-Results: mail-b.sr.ht; dkim=none Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id AB92211F322; Sat, 2 Dec 2023 13:40:33 +0000 (UTC) From: ~lbryndza Date: Sat, 02 Dec 2023 13:12:37 +0100 Subject: [PATCH qemu v3 05/20] Fixing the basic functionality of STM32 timers Message-ID: <170152443229.18048.53824064267512246-5@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <170152443229.18048.53824064267512246-0@git.sr.ht> To: qemu-devel@nongnu.org Cc: Alistair Francis , Peter Maydell MIME-Version: 1.0 Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 2 X-Spam_score: 0.2 X-Spam_bar: / X-Spam_report: (0.2 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~lbryndza Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Lucjan Bryndza The current implementation of timers does not work properly even in basic functionality. A counter configured to report an interrupt every 10ms reports the first interrupts after a few seconds. There are also no properly implemented count up an count down modes. This commit fixes bugs with interrupt reporting and implements the basic modes of the counter's time-base block. Add timer update function using ptimer implementation Signed-off-by: Lucjan Bryndza --- hw/timer/stm32f2xx_timer.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c index 9261090b84..62c98b5f04 100644 --- a/hw/timer/stm32f2xx_timer.c +++ b/hw/timer/stm32f2xx_timer.c @@ -68,6 +68,28 @@ static void stm32f2xx_timer_set_count(STM32F2XXTimerState *s, uint32_t cnt) } } +static void stm32f2xx_timer_update(STM32F2XXTimerState *s) +{ + if (s->tim_cr1 & TIM_CR1_DIR) { + s->count_mode = TIMER_DOWN_COUNT; + } else { + s->count_mode = TIMER_UP_COUNT; + } + + if (s->tim_cr1 & TIM_CR1_CMS) { + s->count_mode = TIMER_UP_COUNT; + } + + if (s->tim_cr1 & TIM_CR1_CEN) { + DB_PRINT("Enabling timer\n"); + ptimer_set_freq(s->timer, s->freq_hz); + ptimer_run(s->timer, !(s->tim_cr1 & 0x04)); + } else { + DB_PRINT("Disabling timer\n"); + ptimer_stop(s->timer); + } +} + static void stm32f2xx_timer_reset(DeviceState *dev) {