diff mbox series

[qemu,v3,05/20] Fixing the basic functionality of STM32 timers

Message ID 170152443229.18048.53824064267512246-5@git.sr.ht
State New
Headers show
Series Fix malfunctioning of T2-T5 timers on the STM32 platform | expand

Commit Message

~lbryndza Dec. 2, 2023, 12:12 p.m. UTC 
From: Lucjan Bryndza <lbryndza.oss@icloud.com>

The current implementation of timers does not work properly
even in basic functionality. A counter configured to report
an interrupt every 10ms reports the first interrupts after a
few seconds.  There are also no properly implemented count up an
count down modes. This commit fixes bugs with interrupt
reporting and implements the basic modes of the counter's
time-base block.

Add timer update function using ptimer implementation

Signed-off-by: Lucjan Bryndza <lbryndza.oss@icloud.com>
---
 hw/timer/stm32f2xx_timer.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
diff mbox series

Patch

diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c
index 9261090b84..62c98b5f04 100644
--- a/hw/timer/stm32f2xx_timer.c
+++ b/hw/timer/stm32f2xx_timer.c
@@ -68,6 +68,28 @@  static void stm32f2xx_timer_set_count(STM32F2XXTimerState *s, uint32_t cnt)
     }
 }
 
+static void stm32f2xx_timer_update(STM32F2XXTimerState *s)
+{
+    if (s->tim_cr1 & TIM_CR1_DIR) {
+        s->count_mode = TIMER_DOWN_COUNT;
+    } else {
+        s->count_mode = TIMER_UP_COUNT;
+    }
+
+    if (s->tim_cr1 & TIM_CR1_CMS) {
+        s->count_mode = TIMER_UP_COUNT;
+    }
+
+    if (s->tim_cr1 & TIM_CR1_CEN) {
+        DB_PRINT("Enabling timer\n");
+        ptimer_set_freq(s->timer, s->freq_hz);
+        ptimer_run(s->timer, !(s->tim_cr1 & 0x04));
+    } else {
+        DB_PRINT("Disabling timer\n");
+        ptimer_stop(s->timer);
+    }
+}
+
 
 static void stm32f2xx_timer_reset(DeviceState *dev)
 {