From patchwork Sat Dec 2 12:21:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ~lbryndza X-Patchwork-Id: 1870927 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SjB4D0Th8z1ySt for ; Sun, 3 Dec 2023 00:44:28 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r9QEy-0005DS-8G; Sat, 02 Dec 2023 08:41:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r9QEt-0005BE-MF for qemu-devel@nongnu.org; Sat, 02 Dec 2023 08:40:59 -0500 Received: from mail-b.sr.ht ([173.195.146.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r9QEq-00006e-K1 for qemu-devel@nongnu.org; Sat, 02 Dec 2023 08:40:58 -0500 Authentication-Results: mail-b.sr.ht; dkim=none Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id E50BC11F367; Sat, 2 Dec 2023 13:40:35 +0000 (UTC) From: ~lbryndza Date: Sat, 02 Dec 2023 13:21:32 +0100 Subject: [PATCH qemu v3 15/20] Fixing the basic functionality of STM32 timers Message-ID: <170152443229.18048.53824064267512246-15@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <170152443229.18048.53824064267512246-0@git.sr.ht> To: qemu-devel@nongnu.org Cc: Alistair Francis , Peter Maydell MIME-Version: 1.0 Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 2 X-Spam_score: 0.2 X-Spam_bar: / X-Spam_report: (0.2 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~lbryndza Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Lucjan Bryndza The current implementation of timers does not work properly even in basic functionality. A counter configured to report an interrupt every 10ms reports the first interrupts after a few seconds. There are also no properly implemented count up an count down modes. This commit fixes bugs with interrupt reporting and implements the basic modes of the counter's time-base block. Add update ARR function Signed-off-by: Lucjan Bryndza --- hw/timer/stm32f2xx_timer.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c index 0678e718a1..800172a3ff 100644 --- a/hw/timer/stm32f2xx_timer.c +++ b/hw/timer/stm32f2xx_timer.c @@ -256,6 +256,15 @@ static void stm32f2xx_update_cnt(STM32F2XXTimerState *s, uint64_t value) ptimer_transaction_commit(s->timer); DB_PRINT("write cnt = %x\n", stm32f2xx_timer_get_count(s)); } + +static void stm32f2xx_update_arr(STM32F2XXTimerState *s, uint64_t value) +{ + s->tim_arr = value & 0xffff; + ptimer_transaction_begin(s->timer); + ptimer_set_limit(s->timer, s->tim_arr, 1); + ptimer_transaction_commit(s->timer); + DB_PRINT("write arr = %x\n", s->tim_arr); +} static void stm32f2xx_timer_write(void *opaque, hwaddr offset, uint64_t val64, unsigned size) {