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[qemu,v3,14/20] Fixing the basic functionality of STM32 timers

Message ID 170152443229.18048.53824064267512246-14@git.sr.ht
State New
Headers show
Series Fix malfunctioning of T2-T5 timers on the STM32 platform | expand

Commit Message

~lbryndza Dec. 2, 2023, 12:21 p.m. UTC 
From: Lucjan Bryndza <lbryndza.oss@icloud.com>

The current implementation of timers does not work properly
even in basic functionality. A counter configured to report
an interrupt every 10ms reports the first interrupts after a
few seconds.  There are also no properly implemented count up an
count down modes. This commit fixes bugs with interrupt
reporting and implements the basic modes of the counter's
time-base block.

Add update cnt function

Signed-off-by: Lucjan Bryndza <lbryndza.oss@icloud.com>
---
 hw/timer/stm32f2xx_timer.c | 8 ++++++++
 1 file changed, 8 insertions(+)
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Patch

diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c
index 010b5b41bd..0678e718a1 100644
--- a/hw/timer/stm32f2xx_timer.c
+++ b/hw/timer/stm32f2xx_timer.c
@@ -248,6 +248,14 @@  static void stm32f2xx_update_egr(STM32F2XXTimerState *s, uint64_t value)
     }
     DB_PRINT("write EGR = %x\n", s->tim_egr);
 }
+
+static void stm32f2xx_update_cnt(STM32F2XXTimerState *s, uint64_t value)
+{
+    ptimer_transaction_begin(s->timer);
+    stm32f2xx_timer_set_count(s, value & 0xffff);
+    ptimer_transaction_commit(s->timer);
+    DB_PRINT("write cnt = %x\n", stm32f2xx_timer_get_count(s));
+}
 static void stm32f2xx_timer_write(void *opaque, hwaddr offset,
                         uint64_t val64, unsigned size)
 {