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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id b19sm7292575pft.74.2020.06.08.07.18.16 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 08 Jun 2020 07:18:17 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 01/15] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions Date: Mon, 8 Jun 2020 07:17:30 -0700 Message-Id: <1591625864-31494-2-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1591625864-31494-1-git-send-email-bmeng.cn@gmail.com> References: <1591625864-31494-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::641; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x641.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng This was done in the virt & sifive_u codes, but sifive_e codes were missed. Remove the riscv_ prefix of the machine* and soc* functions. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/sifive_e.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 472a989..8fab152 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -75,7 +75,7 @@ static const struct MemmapEntry { [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 } }; -static void riscv_sifive_e_init(MachineState *machine) +static void sifive_e_machine_init(MachineState *machine) { const struct MemmapEntry *memmap = sifive_e_memmap; @@ -124,7 +124,7 @@ static void sifive_e_machine_class_init(ObjectClass *oc, void *data) MachineClass *mc = MACHINE_CLASS(oc); mc->desc = "RISC-V Board compatible with SiFive E SDK"; - mc->init = riscv_sifive_e_init; + mc->init = sifive_e_machine_init; mc->max_cpus = 1; mc->default_cpu_type = SIFIVE_E_CPU; } @@ -144,7 +144,7 @@ static void sifive_e_machine_init_register_types(void) type_init(sifive_e_machine_init_register_types) -static void riscv_sifive_e_soc_init(Object *obj) +static void sifive_e_soc_init(Object *obj) { MachineState *ms = MACHINE(qdev_get_machine()); SiFiveESoCState *s = RISCV_E_SOC(obj); @@ -159,7 +159,7 @@ static void riscv_sifive_e_soc_init(Object *obj) TYPE_SIFIVE_GPIO); } -static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) +static void sifive_e_soc_realize(DeviceState *dev, Error **errp) { MachineState *ms = MACHINE(qdev_get_machine()); const struct MemmapEntry *memmap = sifive_e_memmap; @@ -243,26 +243,26 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) &s->xip_mem); } -static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data) +static void sifive_e_soc_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); - dc->realize = riscv_sifive_e_soc_realize; + dc->realize = sifive_e_soc_realize; /* Reason: Uses serial_hds in realize function, thus can't be used twice */ dc->user_creatable = false; } -static const TypeInfo riscv_sifive_e_soc_type_info = { +static const TypeInfo sifive_e_soc_type_info = { .name = TYPE_RISCV_E_SOC, .parent = TYPE_DEVICE, .instance_size = sizeof(SiFiveESoCState), - .instance_init = riscv_sifive_e_soc_init, - .class_init = riscv_sifive_e_soc_class_init, + .instance_init = sifive_e_soc_init, + .class_init = sifive_e_soc_class_init, }; -static void riscv_sifive_e_soc_register_types(void) +static void sifive_e_soc_register_types(void) { - type_register_static(&riscv_sifive_e_soc_type_info); + type_register_static(&sifive_e_soc_type_info); } -type_init(riscv_sifive_e_soc_register_types) +type_init(sifive_e_soc_register_types)